IDT72201L10PF8 IDT, Integrated Device Technology Inc, IDT72201L10PF8 Datasheet - Page 2

• Manufacturer Part Number: IDT72201L10PF8
• Description: IC FIFO 256X9 SYNC 10NS 32-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72201L10PF8

• Function: Synchronous
• Memory Size: 2.3K (256 x 9)
• Data Rate: 100MHz
• Access Time: 11.5ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72201L10PF8

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PIN CONFIGURATION
PIN DESCRIPTIONS
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
Symbol
D
RS
WCLK
WEN1
WEN2/
LD
Q
RCLK
REN1
REN2
OE
EF
PAE
PAF
FF
V
GND
0
CC
0
-D
-Q
8
8
RCLK
REN2
REN1
GND
PAF
PAE
INDEX
D
D
Data Inputs
Reset
Write Clock
Write Enable 1
Write Enable 2/
Load
Data Outputs
Read Enable 1
Read Enable 2
Output Enable
Empty Flag
Programmable
Almost-Empty Flag
Programmable
Almost-Full Flag
Full Flag
Power
Ground
Read Clock
0
1
5
6
7
8
1
2
3
4
Name
TQFP (PR32-1, order code: PF)
32 31 30
9 10 11 12 13 14 15
29 28
TOP VIEW
I/O
O Data outputs for a 9-bit bus.
O When
O When
O When
O When
I
I
I
I
I
I
I
I
I
27 26 25
Data inputs for a 9-bit bus.
When
go HIGH, and
Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write Enable(s) are asserted.
data is written into the FIFO on every LOW-to-HIGH transition WCLK. If the FIFO is configured to have two write
enables,
the FIFO if the
to load and read the programmable flag offsets. If the FIFO is configured to have two write enables,
be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO if the
LOW. If the FIFO is configured to have programmable flags, WEN2/
programmable flag offsets.
When
Data will not be read from the FIFO if the
When
Data will not be read from the FIFO if the
When
state.
FIFO is not empty.
offset at reset is Empty+7.
at reset is Full-7.
is not full.
One +5 volt power supply pin.
If the FIFO is configured to have programmable flags,
The FIFO is configured at reset to have either two write enables or programmable flags. If WEN2/
at reset, this pin operates as a second write enable. If WEN2/
Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when
One 0 volt ground pin.
16
OE
EF
PAE
PAF
FF
RS
REN1
REN1
24
23
22
21
20
19
18
17
WEN1
is LOW, the FIFO is full and further data writes into the input are inhibited. When
is LOW, the FIFO is empty and further data reads from the output are inhibited. When
FF
is set LOW, internal read and write pointers are set to the first location of the RAM array,
is LOW, the data output bus is active. If
is LOW, the FIFO is almost-full based on the offset programmed into the FIFO. The default offset
is LOW, the FIFO is almost-empty based on the offset programmed into the FIFO. The default
and
and
is synchronized to WCLK.
2655 drw 02
PAE
FF
Q
Q
Q
WEN1
WCLK
WEN2/LD
Q
V
must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into
7
5
CC
8
6
REN2
REN2
is LOW.
PAF
and
EF
is synchronized to WCLK.
is synchronized to RCLK.
are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.
are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.
EF
PAE
go LOW. A reset is required before an initial WRITE after power-up.
is synchronized to RCLK.
2
EF
EF
is LOW.
is LOW.
Description
OE
INDEX
REN1
RCLK
REN2
GND
PAE
PAF
OE
is HIGH, the output data bus will be in a high-impedance
D
D
WEN1
0
1
PLCC (J32-1, order code: J)
is the only write enable pin. When
5
6
7
8
9
10
11
12
13
LD
14 15 16 17 18 19 20
4
is LOW at reset, this pin operates as a control
3
LD
TOP VIEW
2
is held LOW to write or read the
REN1
COMMERCIAL AND INDUSTRIAL
1
32 31 30
and
REN2
TEMPERATURE RANGES
29
28
27
26
25
24
23
22
21
OCTOBER 22, 2008
are asserted.
FF
is HIGH, the FIFO
WEN1
RS
WEN1
WCLK
WEN2/LD
V
Q
Q
Q
2655 drw02a
Q
EF
CC
8
7
5
6
FF
LD
is HIGH, the
WEN1
is LOW,
is
and
HIGH
FF
must
PAF
is