IDT7280L12PAG8 IDT, Integrated Device Technology Inc, IDT7280L12PAG8 Datasheet - Page 8

• Manufacturer Part Number: IDT7280L12PAG8
• Description: IC MEM FIFO 256X9 12NS 56-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT7280L12PAG8

• Function: Asynchronous
• Memory Size: 2.3K (256 x 9)
• Data Rate: 50MHz
• Access Time: 12ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 7280L12PAG8

USAGE MODES:
WIDTH EXPANSION
control signals of multiple FIFOs. Status flags (EF, FF and HF) can be detected
from any one FIFO. Figure 13 demonstrates an 18-bit word width by using the
two FIFOs contained in the IDT7280/7281/7282/7283/7284/7285s. Any word
width can be attained by adding FIFOs (Figure 13).
BIDIRECTIONAL OPERATION
system capable of Read and Write operations) can be achieved by pairing
IDT7280/7281/7282/7283/7384/7285s as shown in Figure 16. Both Depth
Expansion and Width Expansion may be used in this mode.
DATA FLOW-THROUGH
and write flow-through mode. For the read flow-through mode (Figure 17),
IDT7280/7281/7282/7283/7284/7285 5V ASYNCHRONOUS FIFO
DUAL 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
Figure 13. Block Diagram of 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18 FIFO Memory Used in Width Expansion Mode
Word width may be increased simply by connecting the corresponding input
Applications which require data buffering between two systems (each
Two types of flow-through modes are permitted, a read flow-through
Figure 12. Block Diagram of One 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 FIFO Used in Single Device Mode
FULL FLAG (FFA)
DATA
RESET (RS)
WRITE (W)
FULL FLAG (FF)
IN
(D)
DATA IN (D)
RESET (RS)
WRITE (W)
(HALF-FULL FLAG)
18
EXPANSION IN (XI)
9
9
XIA
FIFO A
HFA
A or B
FIFO
7280
7281
7282
7283
7284
7285
(HF)
IDT
9
7280/7281/7282/
7283/7284/7285
8
the FIFO permits a reading of a single word after writing one word of data into
an empty FIFO. The data is enabled on the bus in (t
edge of W, called the first write edge, and it remains on the bus until the R line
is raised from LOW-to-HIGH, after which the bus would go into a three-state
mode after t
deassertion and then would be asserted.
of a single word of data immediately after reading one word of data from a
full FIFO. The R line causes the FF to be deasserted but the W line being LOW
causes it to be asserted again in anticipation of a new data word. On the rising
edge of W, the new word is loaded in the FIFO. The W line must be toggled when
FF is not asserted to write new data in the FIFO and to increment the write pointer.
COMPOUND EXPANSION
in a straightforward manner to achieve large FIFO arrays (see Figure 15).
In the write flow-through mode (Figure 18), the FIFO permits the writing
The two expansion techniques described above can be applied together
9
9
FIFO B
HFB
RHZ
XIB
READ (R)
RETRANSMIT (RT)
ns. The EF line would have a pulse showing temporary
DATA OUT (Q)
EMPTY FLAG (EF)
9
3208 drw 14
COMMERCIAL TEMPERATURE RANGE
18
DATA
READ (R)
EMPTY FLAG (EFB)
RETRANSMIT (RT)
3208 drw 15
OUT
WEF
(Q)
JANUARY 13, 2009
+ t
A
) ns after the rising