IMP16C552-CJ68 IMP Inc, IMP16C552-CJ68 Datasheet - Page 15

• Manufacturer Part Number: IMP16C552-CJ68
• Description: Dual Universal Asynchronous Receiver/Transmitter (UART) with 16-BYTE FIFO & Parallel Printer Port
• Manufacturer: IMP Inc

15
this error is associated with the particular
character in the FIFO it applies to. This error
is revealed to the CPU when its associated
character is at the top of the FIFO. The UART
will resynchronize after a Framing Error.
Bits 4:
indicator. Bit 4 is set to a logic 1 whenever the
received data input is held in the spacing
(logic 0 ) state for longer than a full word
transmission time (that is, the total time of
Start bit + data bits + Parity + Stop bits ). The
BI indicator is reset whenever the CPU reads
the contents of the Line Status Register. When
in FIFO mode, BI is associated to the
particular character in the FIFO, and this bit is
set when the associated character is at the
top of the FIFO. When a break occurs, only
one zero character is loaded into the FIFO.
The next character transferred is enable after
SIN goes to the marking state (logic 1 ) and
receives the next valid start bit.
Note: Bits 1 through 4 are the error conditions
that produce a Receiver Line Status interrupt
whenever any of the corresponding conditions
are detected and the interrupt enabled.
Bit 5:
Register empty
indicates that the UART is ready to accept a
new character for transmission. In addition,
this bit causes the UART to issue an interrupt
to the CPU when the Transmit Holding
Register Empty Interrupt enable is set high.
The THRE bit is set to a logic 1 when a
character is transferred from the Transmitter
Holding Register into the Transmitter Shift
Register.
concurrently
Transmitter Holding Register by the CPU. In
the FIFO mode, this bit will be set when XMIT
FIFO is empty, and cleared when as least one
character is written to XMIT FIFO.
Bit 6:
(TEMT) indicator. Bit 6 is set to a logic 1
whenever the Transmitter Holding Register
(THR) and the Transmitter Shift Register
(TSR) are both empty. It is reset to a logic 0
whenever either the THR or the TSR contains
a data character. In the FIFO mode this bit is
set to 1 whenever the transmitter FIFO and
This bit is the Transmitter Empty
This bit is the Break Interrupt (BI)
This is the Transmitter Holding
The
with
bit
(THRE) indicator. Bit 5
the
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408-432-9100/www.impweb.com
logic
of
the
0
shift register are both empty.
Bit 7 :
(LSR7) is a 0. In the FIFO mode it is set when
there is a least one parity error, framing error
or break indication in the FIFO. LSR7 is clear
when the CPU reads the LSR, if there are no
subsequent errors in the FIFO.
Note: The Line Status Register is intended
for read operations only. Writing to this
register is not recommended.
Interrupt Identification Register
In
overhead during data character transfers, the
UART prioritizes interrupts into four levels and
records these in the interrupt Identification
Register.
conditions are as follows :Receiver Line
Status (priority 1), Received Data Ready
(priority 3 ) , and MODEM Status (priority 4).
Information
interrupt is pending and source of that
interrupt is stored in the Interrupt Identification
Register
When addressed during chip select time,
freezes the highest priority interrupt pending
and no other interrupts are acknowledged until
the particular interrupt is serviced by the CPU.
Its contents are indicated in Table VI and are
described below:
Bit 0: This bit can be used in a prioritized or
polled environment to indicate whether an
interrupt is pending when bit 0 is a logic 0 an
interrupt is pending and the IIR contents may
be used as a pointer to the appropriate
interrupts service routine when bit 0 is a logic
1 no interrupt is pending and polling
used)continues
Bit 1,2 : these two bits of IIR are used to
identity the highest priority interrupt pending
(see Table VI)
Bit3 : In the character mode this bit 0 in the
FIFO mode this bit is set along with bit 2 when
a timeout interrupt is pending
Bit 4,5: These two bits of the IIR are always
logic 0
order
(refer to Table VI). Register IIR.
In the Character Mode, this bit
The
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© 2002 IMP, Inc.