IMP16C552-CJ68 IMP Inc, IMP16C552-CJ68 Datasheet - Page 6

• Manufacturer Part Number: IMP16C552-CJ68
• Description: Dual Universal Asynchronous Receiver/Transmitter (UART) with 16-BYTE FIFO & Parallel Printer Port
• Manufacturer: IMP Inc

6
Mnemonic
DTR0*
DTR1*
RTS0*
RTS1*
TXRdy0*
TXRDy1*
Rxrdy0*
RXRdy1
BDO
Pin
type
OUT
OUT
OUT
OUT
OUT
Pin#
25,11
24,12
22,42
9,61
44
Description
Data Terminal Ready :When low this informs the MODEM or data set
that the UART is ready to establish a communication link
DTR0(1)* output signal can be set to an active low by programming bit 0
(DTR) of the MODEM Control Register to a 1.A Master reset operation
sets this inactive (high) state. Loop mode operation holds this signal in
its inactive state
Request To Send: When low this informs the MODEM or data set that
the UART is ready to exchange data. The RTS0(1)* output signal can be
set to an active low by programming bit 1 (RTS)of the MODEM Control
register to a 1.A Master Reset operation sets this signal to its inactive
(high) state . Loop operation holds this signal in its inactive state
Transmitter Ready pins: Transmitter DMA signalling is available through
this pin for each serial channel When operating in the FIFO mode one
of two
operating as in the Character Mode, only DMA mode 0is allowed. Mode
0 supports single transfer multi-transfer DMA where multiple transfers
are made continuously until the XMIT FIFO has been filled
TXRDY mode 0:when in non FIFO mode (FCR3=1) or in the FIFO mode
(FCR0=1,FCR3=0) there are no characters in the XMIT FIFO or XMIT
holding register the TXRDY pin will be low active . once it is activated
the TXRDY0 TXRDY1.pin will go inactive after the first character is
loaded into the XMIT FIFO or holding register
TXRDY MODE 1:In the FIFO Mode (FCR0=1,FCR3=1)if there is at least
one untilled position in the XMIT FIFO, it will go low active. This pin will
become inactive when the XMIT FIFO is completely full
Receiver Ready pins: Receiver DMA signaling is available through this
pin when operating in the FIFO mode
signaling can be selected via FCR3. When operating as in the Character
Mode, only DMA mode O is allowed Mode 0supports single transfer
DMA where a transfer is made between CPU bus cycles Mode 1
supports multiple transfers DMA where multiple transfer are made
continuously until the RCVR FIFO has been emptied
RXRDY Mode 0: When in the FI FO Mode (FCR=0)or in the FIFO Mode
(FCR0=1.FCR3=0)there is at least 1 character in the RCVR FIFO or
RCVR holding register the RXRDY0*, RXRDY1* pin will go low active,
Once it is activated the RXRDY0*, RXRDY1* pin will go inactive when
there are no more characters in the FIFO or holding register
RXRDY MODE 1: in the FIFO mode (FCR0=1,FCR3=1 ) the trigger level
or the timeout has been reached, the RXRDY0*, RXRDY1* pin will go
low active. Once it is activated it will go inactive when there are no more
characters in the FIFO or holding register.
Bus Buffer Output :This goes high whenever the CPU is reading data or
status from either the serial channel or parallel port It can be used to
disable or control direction of a data bus transceiver between the CPU
and the device.
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types of DMA signaling can be selected via FCR3. When
IMP16C552
IMP16C552
one of two types of DMA
The
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