IMP16C552-CJ68 IMP Inc, IMP16C552-CJ68 Datasheet - Page 19

• Manufacturer Part Number: IMP16C552-CJ68
• Description: Dual Universal Asynchronous Receiver/Transmitter (UART) with 16-BYTE FIFO & Parallel Printer Port
• Manufacturer: IMP Inc

19
changed state since the last time it was read
by the CPU.
Bit 2: This bit is the Trailing Edge of Rin
Indicator (TREI) detector. Bit 2 indicates that
the RI input to the chip has changed from a
low to high state since the last time it was
read by the CPU.
Bit 3: This bit is the Delta Received Line
Signal Detector (DRLSD) indicator.
when set to logic 1, indicates that the RLSD
input to the chip has changed state since the
last time it was read by the CPU.
Note: Whenever bit 0, 1, 2, or 3 is set to logic
1, a MODEM Status Interrupt is generated, if
bit 3 (EDSSI) of the interrupt enable register is
set.
Bit 4: This bit is the complement of the Clear
to Send (CTS*) input. This bit is equivalent
to bit RTS of the MODEM control register, if bit
4 of the MCR is set to 1 (loop mode).
Bit 5: This bit is the complement of the Data
Set Ready (DSR)* input.
equivalent to bit DTR of the MODEM control
register, if bit 4 of the MCR is set to 1(loop
mode).
Bit 6: This bit is the complement of the Ring
Indicator (RI)* input. This bit is equivalent to
bit OUT1 of the MODEM control register, if bit
4 the MCR is set to 1 (loop mode).
Bit 7: This bit is the complement of the
Received Line Signal Detect (RLSD) input.
This bit equivalent to bit OUT2 of the MODEM
control register, if bit 4 of the MCR is set to 1
(loop mode).
FIFO Interrupt Mode Operation
When the RCVR FIFO and receiver interrupts
are
interrupts will occur as follows:
A.
The receive data available interrupt will
be issued to the CPU when the FIFO
has reached its programmed trigger
level; it will be cleared as soon as the
FIFO drops below its
enabled,
(FCR0=1,
IER0=1)
This bit is
programmed
408-432-9100/www.impweb.com
RCVR
Bit 3
B.
C.
D.
When RCVR FIFO and receiver interrupts are
enabled, RCVR FIFO timeout interrupts will
occur as follows:
A. A FIFO timeout interrupt will occur, if the
This will cause a maximum character received
to interrupt issued delay of 160 ms at 300
BAUD with a 12 bit character.
B. character times are calculated by using
C. When a timeout interrupt has occurred, it
D. When
-at least one character is in the RCVR
-the most recent serial character received
FIFO.
-the most recent CPU read of the FIFO
following conditions exists:
the RCLK input for a clock signal (this
makes the delay proportional to the baud
rate).
is cleared and the timer is reset when the
CPU reads one character form the RCVR
FIFO.
occurred the ` timeout timer is reset after
a new character is received or after the
was
character times ago (if 2 stop bits are
programmed the second one is included
in this time delay ).
was longer than 4 continuous character
times ago.
trigger level.
The IIR receive data available indication
also occurs when the FIFO trigger level
is reached, and like the interrupt, it is
cleared when the FIFO drops below the
trigger level.
The
(IIR=06), as before, has higher priority
than the received data available (IIR=04)
interrupt.
The data ready bit (LSR bit 0) is set as
soon as a character is transferred from
the shift register to the RCVR FIFO. It
is reset when the FIFO is empty.
longer than 4 continuous
receiver
a
IMP16C552
IMP16C552
timeout
line
interrupt
status
has
interrupt
not
© 2002 IMP, Inc.