UPD160062 NEC, UPD160062 Datasheet

no-image

UPD160062

Manufacturer Part Number
UPD160062
Description
420-OUTPUT TFT-LCD SOURCE DRIVER
Manufacturer
NEC
Datasheet
Document No. S16449EJ1V0DS00 (1st edition)
Date Published July 2003 NS CP(K)
Printed in Japan
DESCRIPTION
based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors
by output of 64 values
common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and
column line inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter
circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity.
panels.
FEATURES
• CMOS level input (2.3 to 3.6 V)
• 420 outputs
• Input of 6 bits (gray scale data) by 6 dots
• Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter (R-DAC)
• Logic power supply voltage (V
• Driver power supply voltage (V
• High-speed data transfer: f
• Output dynamic range V
• Apply for dot-line inversion, n-line inversion and column line inversion
• Output voltage polarity inversion function (POL)
• Input data inversion function (capable of controlling by each input port) (POL21, POL22)
• Current consumption control function (LPC, HPC, Bcont)
• Slim chip
ORDERING INFORMATION
Remark The TCP’s external shape is customized. To order the required shape, please contact one of our sales
Assuring a clock frequency of 45 MHz when driving at 2.3 V, this driver is applicable to SXGA+ standard TFT-LCD
The
Because the output dynamic range is as large as V
µ
µ
PD160062 is a source driver for TFT-LCDs capable of dealing with displays with 64-gray scale. Data input is
PD160062N-×××
Part Number
representatives.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
γ
-corrected by an internal D/A converter and 5-by-2 external power modules.
SS2
CLK
420-OUTPUT TFT-LCD SOURCE DRIVER
+0.1 V to V
(COMPATIBLE WITH 64-GRAY SCALE)
DD1
= 45 MHz (internal data transfer speed when operating at V
DD2
) : 2.3 to 3.6 V
) : 8.0 to 9.0 V
TCP (TAB package)
DD2
Package
–0.1 V
DATA SHEET
SS2
+0.1 V to V
MOS INTEGRATED CIRCUIT
DD2
–0.1 V, level inversion operation of the LCD’s
µ
PD160062
DD1
= 2.3 V)
www.DataSheet4U.com
2002

Related parts for UPD160062

UPD160062 Summary of contents

Page 1

... D/A converter and 5-by-2 external power modules. Because the output dynamic range is as large as V common electrode is rendered unnecessary. Also able to deal with dot-line inversion, n-line inversion and column line inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity ...

Page 2

BLOCK DIAGRAM STHR R,/L CLK STB POL21, ...

Page 3

PIN CONFIGURATION ( PD160062N-xxx: TCP) (Copper Foil Surface, Face-up) STHL ...

Page 4

... R,/ (left shift) : STHL input STHR output 420 1 These refer to the start pulse I/O pins when driver ICs are connected in cascade. Fetching of display data starts when H is read at the rising edge of CLK. R,/ (right shift) : STHR input, STHL output R,/ (left shift) : STHL input, STHR output A H level should be input as the pulse of one cycle of the clock signal ...

Page 5

Pin Symbol Pin Name I/O γ − -corrected power 0 9 supplies − V Logic power supply DD1 − V Driver power supply DD2 − V Logic ground SS1 − V Driver ground SS2 Cautions 1. The ...

Page 6

... For the 2 sets of five 0 63 respectively, input gray scale voltages of the same polarity with respect to the common voltage. When fine gray scale voltage precision is not necessary, there is no need to connect a voltage follower circuit to the supplies and ...

Page 7

... Remark The resistance ratio1 is a relative ratio in the case of setting the minimum resistance value to 1. The resistance ratio2 is a relative ratio in the case of setting the total resistance to 1. Caution There is no connection between V rn Ratio 1 V ’’ ...

Page 8

Figure 5−3. Relationship between Input Data and Output Voltage (POL21, POL22 = L) (Output Voltage 1) V (Output Voltage 2) 0.5 V Input Data 00H 01H 02H V V +(V 1 ...

Page 9

RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN Data format: 6 bits × 2 RGBs (6 dots) Input width: 36 bits (2-pixel data) (1) R,/ (right shift) Output Data ...

Page 10

RELATIONSHIP BETWEEN STB, CLK AND OUTPUT WAVEFORM The output voltage is written to the LCD panel synchronized with the STB falling edge. Figure 8−1. Output Circuit Block Diagram DAC Figure 8−2. Output Circuit Timing Waveform CLK (External input) STB ...

Page 11

CURRENT CONSUMPTION CONTROL FUNCTION µ The PD160062 has a power control function which can switch the bias current of the output amplifier between four levels and a bias control function (Bcont) which can be used to finely control the ...

Page 12

... Bias Current Control Function (Bcont) > possible to fine-control the current consumption by using the bias current control function (Bcont pin). When using this function, connect this pin to the stabilized ground potential (V using this function, leave this pin open. Figure 9−1. Bias Current Control Function (Bcont) Refer to the table below for the percentage of current regulation when using the bias current control function. Table 9− ...

Page 13

ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T = 25° Parameter Symbol Logic Part Supply Voltage V DD1 Driver Part Supply Voltage V DD2 Logic Part Input Voltage V I1 Driver Part Input Voltage V I2 Logic Part Output ...

Page 14

... The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the measured values in the dot checkerboard input pattern. 3. Refers to the current consumption per driver when cascades are connected under the assumption of SXGA+ single-sided mounting (10 units). = −10 to +75°C, V ...

Page 15

V Timing Requirement (T A Parameter Clock Pulse Width PW Clock Pulse High Period PW Clock Pulse Low Period PW Data Setup Time t SETUP1 Data Hold Time t HOLD1 Start Pulse Setup Time t SETUP2 ...

Page 16

CLK(L) CLK CLK( CLK t t SETUP2 HOLD2 STHR (1st Dr SETUP1 HOLD1 D to 409 INVALID ...

Page 17

... RECOMMENDED MOUNTING CONDITIONS The following conditions must be met for soldering conditions of the For more details, refer to the Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html). Please consult with our sales offices in case other soldering process is used case the soldering is done under different conditions. ...

Page 18

... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...

Related keywords