UPD161643 NEC, UPD161643 Datasheet
UPD161643
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UPD161643 Summary of contents
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... The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. ...
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BLOCK DIAGRAM R,/L CLK STVSEL STVR OE1SEL OE1 OE2SEL OE2 CC1 CC1 Remark /xxx indicates active low signal. www.DataSheet4U.com 2 SR87 SR88 SR1 SR2 SR89 SR90 MPX Level Shifter ...
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PIN CONFIGURATION (PAD LAYOUT) Chip size: 2.3 x 7.05 mm Bump size: INPUT/LEFT/RIGHT (include INPUT/OUTPUT/RIGHT side DUMMY OUTPUT (include OUTPUT side DUMMY www.DataSheet4U.com No.94 No.95 Alignment mark 1 ...
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Gate Inputs 70 m pitch Pad No. Pad Name - Alignment Mark1 1 DUMMY 2 DUMMY 3 DUMMY 4 DUMMY 5 DUMMY 6 DUMMY 7 DUMMY 8 DUMMY 9 DUMMY 10 DUMMY 11 DUMMY 12 DUMMY 13 DUMMY 14 DUMMY ...
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Gate Outputs 35 Pad No. Pad Name 96 DUMMY 97 DUMMY 98 DUMMY 99 DUMMY 100 DUMMY 101 DUMMY 102 O176 103 O175 104 O174 105 O173 106 O172 107 O171 108 O170 109 O169 110 O168 111 O167 112 ...
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Pad No. www.DataSheet4U.com 6 Table 2 1. Pad Layout (3/4) Gate Outputs 35 m pitch Pad Name X [mm] 226 O52 0.8650 227 O51 0.9950 228 O50 0.8650 229 O49 0.9950 230 O48 0.8650 231 O47 0.9950 232 O46 0.8650 ...
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Gate Left 600 Pad No. Pad Name 94 DUMMY 95 DUMMY Pad No. Pad Name - Alignment Mark2 www.DataSheet4U.com Table 2 1. Pad Layout (4/4) m pitch X [mm] Y [mm] Pad No. -0.3000 3.3925 284 0.3000 3.3925 285 X ...
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... OE2SEL = L). However, shift register is not cleared. Moreover, output enable operation is asynchronous on a clock. Connect with GOE2 pin of sauce driver. 32, 33 Input This pin selects effective level of OE2 pin. ...
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... Negative power supply for output buffer. Negative power supply for Liquid crystal Positive power supply for logic circuit Connect to the system ground. 28, 34, 40 Pull-up power supply for mode setting pins (R,/L, STVSEL, OE1SEL, OE2SEL). 31, 37 Pull-down power supply for mode setting pins (R,/L, STVSEL, OE1SEL, OE2SEL) ...
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TIMING CHART The timing chart in each condition is shown as follows. R,/ STVSEL = L, OE1SEL = L, OE2SEL = L 1 CLK OE1 OE2 STVR 176 STVL (O ...
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R,/ STVSEL = H, OE1SEL = L, OE2SEL = H 1 CLK OE1 OE2 STVR 176 STVL ( R,/ STVSEL = ...
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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T A Parameter Supply Voltage Supply Voltage Supply Voltage Supply Voltage Supply Voltage Note Input Voltage Operating Ambient Temperature Storage Temperature Note R,/L, CLK, STVR, STVL, OE1, OE2, STVSEL, OE1SEL, OE2SEL Caution Product quality ...
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... PLH3 pF, PHL4 L OE2 On t PLH4 TLH L t THL When connected in cascade CLK = 2 CC1 T Symbol Condition PW CLK(H) PW CLK(L) PW OE1, OE2 OE t STVR (STVL) CLK SETUP t CLK STVR (STVL) HOLD = (10 to 90%) ...
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Switching Characteristics Waveform (R,/ STVSEL = L, OE1SEL = L, OE2SEL = L) PW CLK(H) CLK 50% STVR (STVL) STVL (STVR OE1 50% www.DataSheet4U.com t PHL3 O n OE2 50% t PLH4 1/f ...
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... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...