AN1250 STMicroelectronics, AN1250 Datasheet - Page 2

• Manufacturer Part Number: AN1250
• Description: STA014/STA015 MPEG LAYER III DECODER AND ADPCM CODEC
• Manufacturer: STMicroelectronics

AN1250 APPLICATION NOTE
can be selected for the compressed output data stream in order to reduce sensitiveness to bitstream errors
while decoding and to enable fast-forward/backward capabilities. Embedded in the device a digital volume at-
tenuator and a dual-band equalizer are available, eliminating the hassle and additional cost of an external audio
processor. The device is fully operated using the standard I2C bus: interface configuration, PLL setup, operation
mode and volume / tones settings can be easily programmed writing to some specific register. It’s also possible
to access a small ‘DSP development RAM’ (256 words) in order to modify the firmware code adding, eventually
specific functions or requirements.
Please contact the local ST branch to get additional information about
2. ADPCM DECODING
ADPCM decoding is always accomplished using the SDI input interface: data must be transmitted to the device
in the same way (and with the same configuration options) as an MP3 stream. Before starting the decoding pro-
cess the ADPCM engine must be properly configured in order to meet encoded bitstream syntax and charac-
teristics. The configuration phase involves the following registers:
When the decoding phase is ongoing it’s possible to adjust the volume and tone control of the output signal
using the following registers:
3. ADPCM ENCODING
STA014/STA015 can be configured in order to get the data to be compressed from two different interfaces: SDI
and ADC.ADC interface can be programmed in order to accept most analog to digital converter formats, includ-
ing different word and slot length. The oversampling clock for the converter is generated by STA014/STA015
and will be automatically switched to the proper frequency according to the programmed sample rate and over-
sampling ratio. SDI interface is the same input interface used to feed MP3 bitstream. It’s based on a simple 2-
wire bus (SCKR and SDI) plus a feedback line (DATA_REQ) used to return embedded FIFO buffer status. Data
must be sent MSb first and in 2’s complement. To retrieve encoded data two different interfaces can be used
as well: I2C and GPSO.This result in 4 different possible configurations to operate the device as an ADPCM
encoding engine: each mode will be briefly explined in the following pages.
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ADPCM_FRAMSE_SIZE (addr. BDh)
ADPCM_SAMPLE_FREQ (addr. 53h)
ADPCM_CONFIG (addr. B8h)
TREBLE_FREQUENCY_LOW (addr. 77h)
TREBLE_FREQUENCY_HIGH (addr. 78h)
TREBLE_ENHANCE (addr. 7Bh)
BASS_FREQUENCY_LOW (addr. 79h)
BASS_FREQUENCY_HIGH (addr. 7Ah)
BASS_ENHANCE (addr. 7Ch)
TONE_ATTEN (addr. 7Dh) (this single control is used for both left and right channels)