AN1250 STMicroelectronics, AN1250 Datasheet - Page 4

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AN1250

Manufacturer Part Number
AN1250
Description
STA014/STA015 MPEG LAYER III DECODER AND ADPCM CODEC
Manufacturer
STMicroelectronics
Datasheet
AN1250 APPLICATION NOTE
Figure 3. Mode 0 flow chart
3.2 Mode 1 (from ADC to GPSO)
Figure 4. Mode 1 block diagram
When the device is configured in mode 1 the ADC interface is selected for incoming data and the GPSO inter-
face for encoded output data. The GPSO_REQ signal should be connected to an interrupt source of the micro-
controller; MCU should then provide the GPSO clock to retrieve encoded data.
The configuration shown in Table 3 can be used to setup the device with G721 codec and for an 8kHz, 16 bit
stereo input stream with frame packing capability.
4/21
MCU
SDI (for decoding)
GPSO_SCKR
GPSO_DATA
GPSO_REQ
LRCK_ADC
0
D00AU1183
READ 18 BYTES FROM
ADPCM_DATA_READY
ADPCM_DATA_READY
CLEAR REGISTER
SCK_ADC
READ REGISTER
ADPCM_DATA_xx
SEND 1 BYTE
(0x40 .. 0x51)
STA015
LFBGA64
TQFP44
(0x52)
(0x52)
1
ADC
SDI_ADC
LRCKT
SCKT
OCLK
SDO
D00AU1184
DAC

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