AN1250 STMicroelectronics, AN1250 Datasheet - Page 5

• Manufacturer Part Number: AN1250
• Description: STA014/STA015 MPEG LAYER III DECODER AND ADPCM CODEC
• Manufacturer: STMicroelectronics

Table 3. Mode 1 (G721, 8kHz, 16 bit stereo + frame) configuration
Figure 5. Mode 2 block diagram
This functional mode will enable ADC input interface for incoming data and I2C for encoded output data. Once
18 new ADPCM encoded data bytes are available an interrupt is issued and the ADPCM_DATA_READY is set
to 1. The MCU must start reading the 18 ADPCM_DATA_xx registers as soon as the interrupt signal has been
received and, after that, must execute the following two operations:
3.3 Mode 2 (from ADC to I2C)
– clear ADPCM_DATA_READY (0x52)
– write 1 in CMD_INTERRUPT register (0x16)
Address
185
187
192
184
114
16
83
77
19
IRQ LINE IS:
SO28
TQFP44
LFBGA
:pin 28 (DATA_REQ)
:pin 35 (GPIO_STROBE)
:pin C2 (GPIO_STROBE)
pin 28 (DATA_REQ)
pin 28 (DATA_REQ)
MCU
ADPCM_SAMPLE_FREQ
SDI (for decoding)
ADPCM_CONFIG
GPSO_ENABLE
SOFT_RESET
ADC_ENABLE
CHIP_MODE
IRQ
LRCK_ADC
I
ADC_WLEN
2
C
Name
PALY
RUN
SCK_ADC
STA015
LFBGA64
TQFP44
SO28
ADC
SDI_ADC
LRCKT
SCKT
OCLK
AN1250 APPLICATION NOTE
SDO
D00AU1185
2 (encoder mode)
3 (decoder mode)
0 (encoder mode)
1 (decoder mode)
DAC
Value
15
11
1
1
1
2
1
5/21