UPD78F9418A NEC, UPD78F9418A Datasheet - Page 139

• Manufacturer Part Number: UPD78F9418A
• Description: (UPD7894xxA) 8-Bit Single Chip Microcontrollers
• Manufacturer: NEC

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9.4.2 Operation as interval timer
respectively, the watchdog timer also operates as an interval timer that repeatedly generates an interrupt at time
intervals specified by a preset count value.
(TCL2). The watchdog timer starts operation as an interval timer when the RUN bit (bit 7 of WDTM) is set to 1.
generated. The priority of INTWDT is set as the highest of all the maskable interrupts.
before entering the STOP mode to clear the interval timer, and then execute the STOP instruction.
When bit 4 (WDTM4) and bit 3 (WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1,
Select the count clock (or interval time) by setting bits 0 to 2 (TCL20 to TCL22) of timer clock selection register 2
In the interval timer mode, the interrupt mask flag (TMMK4) is valid, and a maskable interrupt (INTWDT) can be
The interval timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to 1
Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (when the watchdog timer mode is selected), the
TCL22
f
X
0
0
1
1
: Main system clock oscillation frequency
2. The interval time immediately after the setting by WDTM may be up to 0.8% shorter than the
interval timer mode is not set, unless the RESET signal is input.
set time.
TCL21
0
1
0
1
TCL20
0
0
0
0
Table 9-5. Interval Time of Interval Timer
CHAPTER 9 WATCHDOG TIMER
2
2
2
2
11
13
15
17
× 1/f
× 1/f
× 1/f
× 1/f
User’s Manual U13952EJ3V0UD
X
X
X
X
Interval Time
410 µ s
1.64 ms
6.55 ms
26.2 ms
Operation at f
X
= 5.0 MHz
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