UPD78F9418A NEC, UPD78F9418A Datasheet - Page 274

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UPD78F9418A

Manufacturer Part Number
UPD78F9418A
Description
(UPD7894xxA) 8-Bit Single Chip Microcontrollers
Manufacturer
NEC
Datasheet

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274
CALL
CALLT
RET
RETI
PUSH
POP
MOVW
BR
BC
BNC
BZ
BNZ
BT
BF
DBNZ
NOP
EI
DI
HALT
STOP
Mnemonic
Remark
One instruction clock cycle is one CPU clock cycle (f
register (PCC).
!addr16
[addr5]
PSW
rp
PSW
rp
SP, AX
AX, SP
!addr16
$addr16
AX
$saddr16
$saddr16
$saddr16
$saddr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
B, $addr16
C, $addr16
saddr, $addr16
Operands
CHAPTER 20 INSTRUCTION SET
Bytes
User’s Manual U13952EJ3V0UD
3
1
1
1
1
1
1
1
2
2
3
2
1
2
2
2
2
4
4
3
4
4
4
3
4
2
2
3
1
3
3
1
1
Clocks
10
10
10
10
10
10
6
8
6
8
2
4
4
6
8
6
6
6
6
6
6
6
6
8
8
6
6
8
2
6
6
2
2
(SP − 1) ← (PC + 3)
PC ← addr16, SP ← SP − 2
(SP − 1) ← (PC + 1)
PC
PC
PC
PC
PSW ← (SP + 2), SP ← SP + 3, NMIS ← 0
(SP − 1) ← PSW, SP ← SP − 1
(SP − 1) ← rp
PSW ← (SP), SP ← SP + 1
rp
SP ← AX
AX ← SP
PC ← addr16
PC ← PC + 2 + jdisp8
PC
PC ← PC + 2 + jdisp8 if CY = 1
PC ← PC + 2 + jdisp8 if CY = 0
PC ← PC + 2 + jdisp8 if Z = 1
PC ← PC + 2 + jdisp8 if Z = 0
PC ← PC + 4 + jdisp8 if (saddr.bit) = 1
PC ← PC + 4 + jdisp8 if sfr.bit = 1
PC ← PC + 3 + jdisp8 if A.bit = 1
PC ← PC + 4 + jdisp8 if PSW.bit = 1
PC ← PC + 4 + jdisp8 if (saddr.bit) = 0
PC ← PC + 4 + jdisp8 if sfr.bit = 0
PC ← PC + 3 + jdisp8 if A.bit = 0
PC ← PC + 4 + jdisp8 if PSW.bit = 0
B ← B−1, then PC ← PC + 2 + jdisp8 if B ≠ 0
C ← C−1, then PC ← PC + 2 + jdisp8 if C ≠ 0
(saddr) ← (saddr) − 1, then
PC ← PC + 3 + jdisp8 if (saddr) ≠ 0
No Operation
IE ← 1 (Enable interrupt)
IE ← 0 (Disable interrupt)
Set HALT mode
Set STOP mode
H
H
L
H
H
H
← (SP + 1), rp
← (00000000, addr5), SP ← SP − 2
← (00000000, addr5 + 1),
← (SP + 1), PC
← (SP + 1), PC
← A, PC
CPU
) selected by the processor clock control
L
H
, (SP − 2) ← rp
← X
L
Operation
← (SP), SP ← SP + 2
H
H
L
L
, (SP − 2) ← (PC + 3)
, (SP − 2) ← (PC + 1)
← (SP),
← (SP), SP ← SP + 2
L
, SP ← SP − 2
L
L
,
,
R
R
Z AC CY
Flag
R R
R R

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