UPD98405 NEC, UPD98405 Datasheet - Page 5

• Manufacturer Part Number: UPD98405
• Description: 155M ATM INTEGRATED SAR CONTROLLER
• Manufacturer: NEC

PIN NAME
ABRT_B
ACK64_B
AD63-AD0
AGND
ASEL_B
ATTN_B
AV
BE3_B-BE0_B
CA18-CA0
CBE3_B-CBE0_B
CD31-CD0
CLK
COE_B
CPAR3-CPAR0
CWE_B
DEVSEL_B
DR/W_B
EMPTY_B/RCLAV
ERR_B
E2PCLK
E2PCS
E2PDI
E2PDO
FRAME_B
FULL_B/TCLAV
GND
GNT_B
HGND
HV
IDSEL
INITD
INTR_B
IRDY_B
JCK
JDI
JDO
JMS
JRST_B
OE_B
PAR
PAR3-PAR0
PAR64
PCBE7_B-PCBE0_B: Bus Command and Byte Enables
PCI_MODE
DD3
DD3
: Abort
: Acknowledge 64-bit Transfer
: Address/Data
: Ground for Analog Part
: Slave Address Select
: Attention
: +3.3 V Power Supply for
: Byte Enable
: Control Memory Address
: Local Port Byte Enable
: Control Memory Data
: Clock
: Control Memory Output Enable
: Control Memory parity
: Control Memory Write Enable
: Device Select
: DMA Read/Write
: PHY Empty/Rx Cell Available
: Error
: Clock for EEPROM
: EEPROM Chip Select
: Serial Data Input from EEPROM
: Serial Data Output to EEPROM
: Cycle Frame
: PHY Buffer full/Tx Cell Available
: Ground for Digital Part
: Grant
: Ground for High-Speed Part
: +3.3 V Power Supply for
: ID Select
: Initialization Disable
: Interrupt
: Initiator Ready
: JTAG Test Pin
: JTAG Test Pin
: JTAG Test Pin
: JTAG Test Pin
: JTAG Test Pin
: Output Enable
: Parity
: Bus Party
: Parity 64 bits
: PCI Mode
Analog Part
High-Speed Part
Data Sheet S12689EJ2V0DS00
PERR_B
PHCE_B
PHINT_B
PHOE_B
PHRST_B
PHR/W_B
PHYALM
RCLK
RCIC
RCIT
RDIC
RDIT
PDY_B
REFCLK
RENBL_B
REQ64_B
REQ_B
RGND
ROMA15-ROMA0: Expansion ROM Address
ROMCS_B
RST_B
RV
Rx7-Rx0
SCLK
SD
SEL_B
SERR_B
SIZE2-SIZE0
SR/W_B
STOP_B
TCLK
TDOC
TDOT
TENBL_B
TEST
TFKC
TFKT
TRDY_B
Tx7-Tx0
V
V
ROMD7-ROMD0 : Expansion ROM Input Data
ROMOE_B
RSOC
TSOC
DD3
DD5
DD3
: Parity Error
: PHY Chip Enable
: PHY Output Enable
: PHY Read/Write
: Physical Alarm
: Receive Clock
: Receive Clock Input Complement
: Receive Clock Input True
: Receive Data Input Complement
: Receive Data Input True
: Target Ready
: Reference Clock
: Receive Enable
: Request 64-bit Transfer
: Request
: Ground for Receive PLL Part
: Expansion ROM Chip Select
: Reset
: +3.3 V Power Supply for Receive
: Receive Data Bus
: SAR System Clock
: Signal Detect
: Slave Select
: System Error
: Slave Read /Write
: Stop
: Transmit Clock
: Transmit Data Output Complement
: Transmit Data Output True
: Transmit Enable
: Test Mode Pin
: Transmit Reference Clock Complement
: Transmit Reference Clock True
: Target Ready
: Transmit Data Bus
: +3.3 V Power Supply for Digital Part
: +5 V Power Supply for Digital Part
: PHY Interrupt
: PHY Reset
: Expansion ROM Output Enable
: Receive Start Cell
: Burst Size
: Transmit Start of Cell
PLL Part
PD98405
5