CY28447 ETC, CY28447 Datasheet
CY28447
Available stocks
Related parts for CY28447
CY28447 Summary of contents
Page 1
... Pin Configuration VDD_SRC 53 SRCC_2 SRCT_2 52 SRCC_1 51 SRCT_1 50 VDD_SRC 49 48 SRCC_0 / LCD100MC 47 SRCT_0 / LCD100MT CY28447 46 CLKREQ1# FSB/TEST_MODE 45 DOT96C / 27M_SS 44 DOT96T / 27M_NSS 43 VSS_48 42 41 48M / FSA 40 VDD_48 VTT_PWRGD CLKREQ7# 38 PCIF0/ITP_SEL Page www ...
Page 2
... Spread and Non-spread) (sampled on the VTT_PWRGD# assertion). FCTS DOT96T 1 27M_NSS 3.3V LVTTL input to enable SRC10 or CPU2_ITP / 33-MHz clock output. SE (sampled on the VTT_PWRGD# assertion CPU2_ITP SRC10 CY28447 Description when VTT_PWRGD# is IMFS_C ,V ,V specifi- ILFS_C IMFS_C ...
Page 3
... SRC PCIF/PCI 27MHz 100 MHz 33 MHz 27 MHz 100 MHz 33 MHz 27 MHz 100 MHz 33 MHz 27 MHz 100 MHz 33 MHz 27 MHz Description CY28447 Description REF0 DOT96 USB 14.318 MHz 96 MHz 48 MHz 14.318 MHz 96 MHz 48 MHz 14.318 MHz 96 MHz 48 MHz 14.318 MHz 96 MHz 48 MHz ...
Page 4
... Byte Read Protocol Bit Description 1 Start 8:2 Slave address – 7 bits 9 Write 10 Acknowledge from slave 18:11 Command Code – 8 bits 19 Acknowledge from slave 20 Repeated start 27:21 Slave address – 7 bits 28 Read 29 Acknowledge from slave 37:30 Data from slave – 8 bits 38 NOT Acknowledge 39 Stop CY28447 Page ...
Page 5
... PLL1 (CPU PLL) Spread Spectrum Enable 0 = Spread off Spread on Description PCI4 Output Enable 0 = Disabled Enabled PCI3 Output Enable 0 = Disabled Enabled PCI2 Output Enable 0 = Disabled Enabled PCI1 Output Enable 0 = Disabled Enabled Reserved, Set = 1 Reserved, Set = 1 CPU[T/C]2 Output Enable 0 = Disabled (Hi-Z Enabled Reserved, Set = 1 CY28447 Page ...
Page 6
... Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP# asserted CPU[T/C]0 Stop Drive Mode 0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP# asserted SRC[T/C][9:1] PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted CPU[T/C]2 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted CY28447 Page ...
Page 7
... Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Description RESERVED, Set = 0 RESERVED, Set = 0 RESERVED, Set = 0 RESERVED, Set = 0 RESERVED, Set = 0 USB_48MHz Output Drive Strength 0= Low, 1= High RESERVED, Set = 1 PCIF0 Output Drive Strength 0 = Low High CY28447 Page ...
Page 8
... Allow control of SRC[T/C]9 with assertion of SW PCI_STP Free running Stopped with PCI_STP# Allow control of SRC[T/C]8 with assertion of SW PCI_STP Free running Stopped with PCI_STP# RESERVED RESERVED RESERVED RESERVED 27-MHz (spread and non-spread) Output Drive Strength 0 = Low High RESERVED RESERVED Set = 0 RESERVED CY28447 Description Description Description Page ...
Page 9
... AT Parallel The CY28447 requires a Parallel Resonance Crystal. Substi- tuting a series resonance crystal will cause the CY28447 to operate at the wrong frequency and violate the ppm specifi- cation. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading ...
Page 10
... CLKREQ# are to be stopped after their next transition. The final state of all stopped DIF signals is LOW, both SRCT clock and SRCC clock outputs will not be driven. CY28447 – ( ...
Page 11
... Figure example showing the relationship of clocks coming up. It should be noted that 96_100_SSC will follow the DOT waveform is selected for 96 MHz and the SRC waveform when in 100-MHz mode. Tstable <1.8 ms Tdrive_PWRDN# <300 μs, >200 mV CY28447 Page ...
Page 12
... The maximum latency from the deassertion to active outputs is no more than two CPU clock cycles. Figure 6. CPU_STP# Assertion Waveform Tdrive_CPU_STP#,10 ns>200 mV Figure 7. CPU_STP# Deassertion Waveform CY28447 1.8 ms Page ...
Page 13
... PCI_STP# going LOW Figure 10.) The PCIF clocks will not be affected by this pin if their corresponding control bit in the SMBus register is set to allow them to be free running. PCI_STP# PCI_F PCI SRC 100MHz Rev 1.0, November 20, 2006 ). (See SU Tsu Figure 10. PCI_STP# Assertion Waveform CY28447 1.8mS Page ...
Page 14
... VTT_PW RGD# State 1 State 2 On Figure 12. VTT_PWRGD# Timing Diagram S1 VTT_PWRGD# = Low Delay >0.25mS S3 VDD_A = off Normal Operation VTT_PWRGD# = toggle Figure 13. Single-ended Load Configuration CY28447 Device is not affected, VTT_PW RGD# is ignored State Sample Inputs straps Wait for <1.8ms Enable Outputs Page ...
Page 15
... Except internal pull-up resistors, 0 < Except internal pull-down resistors, 0 < – max. load in low drive mode per Figure 15 and Figure 17 @133 MHz PD asserted, Outputs Driven PD asserted, Outputs Tri-state CY28447 Min. Max. Unit –0.5 4.6 V –0.5 4.6 V –0 0.5 VDC DD – ...
Page 16
... Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX Measured from V = 0.175 0.525V OH Determined as a fraction of 2*(T – T )/( CY28447 Min. Max. Unit 47.5 52.5 % 69.841 71.0 ns – 10.0 ns – 500 ps – 300 ppm 9.997001 10.00300 ns 7 ...
Page 17
... OX OX Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX CY28447 Min. Max. Unit 660 850 mV –150 – mV 250 550 mV – HIGH 0.3 – ...
Page 18
... Measured at crossing point V OX Measured from V = 0.175 0.525V OH Determined as a fraction of 2*(T – T )/( Math averages Figure 17 Math averages Figure 17 See Figure 17. Measure SE Measurement at 1.5V CY28447 Min. Max. Unit 175 700 ps – – 125 ps – 125 ps 660 850 mV –150 – mV ...
Page 19
... Measured between 0.8V and 2.0V Measurement at 1.5V Measured at crossing point V OX Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.0V Measurement at 0.8V Measured between 0.8V and 2.0V Measurement at 1.5V Measured at crossing point V OX Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V CY28447 Min. Max. Unit 20.83125 20.83542 ns 20.48125 21.18542 ns 8.094 11.100 ns 7.694 11.100 ns 1.0 2.0 V/ns – ...
Page 20
... Ω Ω Ω CY28447 Point Point Point M easurem ent P oint M easurem ent P oint M easurem ent P oint M easurem ent P oint M easurem ent ...
Page 21
... Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Rev 1.0, November 20, 2006 Package Type 72-Lead QFN (Punch Version) LF72A CY28447 - Product Flow Commercial, 0° to 85°C Commercial, 0° to 85°C Page ...