AN2244 Freescale Semiconductor / Motorola, AN2244 Datasheet - Page 14

• Manufacturer Part Number: AN2244
• Description: Interconnecting Two MSC8101ADS Boards Across a 60x-Compatible Bus to the Host Interface
• Manufacturer: Freescale Semiconductor / Motorola

Hardware Timings
4.6 Host DMA Channels
5
14
Hardware Timings
Each DMA channel is enabled by setting the ACTV bit in the configuration register associated with that
channel. Here, the activation of the DMA channels is enclosed in an infinite loop so we can monitor and
test the results of the transfer. The loop consists of the following basic steps:
1. Activate Transfer 1 (Host Transmit) DMA Channels 0 and 1.
2. Activate Transfer 2 (Host Receive) DMA Channels 2 and 3.
3. Wait for the DMA transfers to complete.
4. Compare the data received with that transmitted and record any discrepancies.
5. Increment the contents of the first transmit test pattern location so that the same data is not sent
repeatedly. This is the basic operation of the host HDI16 DMA transfer mechanism.
The host MSC8101 UPM-controlled bus and the HDI16 MSC8101 host interface are both programmable.
Careful programming of the host MSC8101 chip select registers and UPM can accommodate the HDI16
MSC8101 host port timings. The timings in Table 1 are based on an implementation with a 40 MHz host
MSC8101 60x-compatible bus-to-200 MHz HDI16 MSC8101. On any bus access the critical timing for
both reads and writes is typically the data latch point. For the UPM-based read access, the host MSC8101
has the flexibility to latch data on a rising or falling
here to latch the HDI16 data into the host MSC8101 as soon as possible. After the data is latched, an
appropriate HDI16 host interface data hold time is ensured before the data strobe (
(
with
attention is given to both the host read and write access strobe (
The HDI16 MSC8101 specifies some restrictions for consecutive register access, which results in a
hold-off negation time for the read and write access strobes. Rather than restrict the firmware to avoid
consecutive bus accesses to host port registers, the negation hold-off times are accommodated in the
UPM hardware interface settings. Additional clocks are built into the end of UPM-based cycle, giving
appropriate time before the next bus cycle starts.
For an application with a 40 MHz host MSC8101 60x-compatible bus and a 200 MHz HDI16 MSC8101,
the host port read and write accesses are both five 40 MHz clocks. The timings are based on a buffered
connection between the host MSC8101ADS and the HDI16 MSC8101ADS host port. The timings can be
readily adapted to allow external decode logic to be added to support chip selects for a larger number of
DSP HDI16 host ports.
Figure 6 and Figure 7 represent the various signals at both the host side (60x) and the DSP side (HDI16)
of the interface.
Note:
CS1
Transfer Error Address Status Register (DTEAR) are cleared by writing a value of one (1) to all the
bits, and the DMA Pin Configuration Register (DPCR) bits are cleared because we do not require it.
CS
) are negated. For the UPM-based write access, the critical action is enveloping the
asserted to ensure a proper write data hold time after latching by the HDI16 host port. Special
For best viewing results, view Figure 6 and Figure 7 online using a zoom factor of 300 percent.
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CLKOUT
edge. The falling
DS
) negation times (
CLKOUT
DS
HDS
) and Chip Select
DS
edge is used
assertion).
assertion