AN2244 Freescale Semiconductor / Motorola, AN2244 Datasheet - Page 3

• Manufacturer Part Number: AN2244
• Description: Interconnecting Two MSC8101ADS Boards Across a 60x-Compatible Bus to the Host Interface
• Manufacturer: Freescale Semiconductor / Motorola

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2.1 Host Memory Controller
2.2 HDI16 Host Interface
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For details on the MSC1810ADS board, consult the MSC8101ADS User’s Manual.
System Bus–HDI16 Host Interface
Also provided are the following:
• The register settings for these modules as used by this application (Section 7, Source Code Files,
• The necessary hardware connections between the host MSC8101 device and the HDI16 MSC8101
• The physical connections for interfacing the host and HDI16 MSC8101 devices are described
• Example source code presented in two parts, one for the host MSC8101 device and one for the HDI16
To understand the function of the parallel control interface between the host MSC8101 system bus and
the HDI16 MSC8101 host interface, it is important to know the device requirements on each side.
The sole function of the memory controller SDRAM machine is to enable back-to-back memory read or
write operations using page mode, pipelined operation, and bank interleaving for high-performance
systems. GPCM-based chip selects interface predominantly to simple asynchronous devices such as
ROM, Flash memory, SRAM, and so on. A GPCM-derived chip select ensures a glueless interface to
such devices over a range of port sizes (8, 16, and 32-bit) and speed grades. However, as compared to the
GPCM, the UPM offers much more flexibility in timing to target a broader range of system devices, and
it offers access to more peripherals, making it more suited to our application. Through the
UPM-controlled memory interface, software can define the chip selects and control strobes on each bus
clock to a 1/4 clock and 1/2 clock granularity, respectively. Developers commonly use this flexibility for
user-defined interfaces to application-specific integrated circuits (ASICs) or, as in our implementation
example, to DSPs. The UPM-defined interface can be used with any of the host MSC8101 eight chip
selects to give a programmable port size and strobe generation matching that required by the HDI16
MSC8101.
The HDI16 host interface has two sets of 16-bit wide registers, one set visible only within the MSC8101
and the other set visible only to the external host processor. Figure 2 illustrates the relationship between
the two sides. All HDI16 registers are mapped directly onto the MSC8101 QBus, and the transmit and
receive FIFOs are mapped onto the DMA data bus so that the DMA controller can access them directly
without intervention by the SC140 core. The QBus, which is part of the SC140 extended core interface, is
a high-speed pipeline bus with separate address and data phases. It is a single-master bus with the same
frequency as the SC140 core. The MSC8101 peripherals, in particular the HDI16 interface, are slaves to
the QBus.
Software Flow, and Register Settings).
device.
specifically for Motorola’s MSC8101 Application Development System (MSC8101ADS) (Section 6).
The MSC8101ADS board is a general development platform with the MSC8101 device installed in a
socket, on-board Flash and SDRAM memory, plus communication transceivers for Fast Ethernet,
ATM 155-Uni, E1/T1, RS-232, and a Crystal stereo audio codec. With this system, developers can start
developing software or use the schematics as a reference for their own system development.
MSC8101 device. These transfers are not optimized. The source code is presented for illustrative
purposes, and not for use as an HDI16 driver.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
System Bus–HDI16 Host Interface
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