AN2244 Freescale Semiconductor / Motorola, AN2244 Datasheet - Page 20

• Manufacturer Part Number: AN2244
• Description: Interconnecting Two MSC8101ADS Boards Across a 60x-Compatible Bus to the Host Interface
• Manufacturer: Freescale Semiconductor / Motorola

Source Code Files, Software Flow, and Register Settings
20
MSC8101ADS BCSR (0x40000000)
MSC8101 Application Development System User’s
Manual, section on “Board Control and Status
Registers” in the chapter on Support Information
HDI16 Host Port Control Register (HPCR)
(0x0081)
“Core-Side Programming Model” in the chapter on
the Host Interface (HDI16)
HDI16 Host Control Register (HCR)
(0x8000 | 0x0000)
“Core-Side Programming Model” in the chapter on
the Host Interface (HDI16)
PIC Interrupt Pending Register B (IPRB)
(0x0004)
“Interrupts Programming Model” in the chapter on
the Interrupt Scheme
Edge/Level-Triggered Interrupt Priority Register E
(ELIRE)
(0x0300)
“Interrupts Programming Model” in the chapter on
the Interrupt Scheme
DMA Channel 0 – BD_ADDR (0x02000000 +
Message Offset)
“DMA Programming Model” in the chapter on DMA
DMA Channel 0 – BD_SIZE
(0x20)
“DMA Programming Model” in the chapter on DMA
DMA Channel 0 – BD_ATTR (0x80000000)
“DMA Programming Model” in the chapter on DMA
DMA Channel 0 – BD_BSIZE
(0)
“DMA Programming Model” in the chapter on DMA
DMA Channel 0 – DCHCR (0x80004005)
Section on the “DMA Programming Model” in the
chapter on DMA
DMA Channel 1 – BD_ADDR (0x02000000 +
Message Offset)
“DMA Programming Model” in the chapter on DMA
DMA Channel 1 – BD_SIZE
(0x20)
“DMA Programming Model” in the chapter on DMA
DMA Channel 1 – BD_ATTR (0x80000010)
“DMA Programming Model” in the chapter on DMA
DMA Channel 1 – BD_BSIZE
(0)
“DMA Programming Model” in the chapter on DMA
Table 6 and Table 7 present the register settings for the HDI16 MSC8101 device and the host MSC8101
device. Unless indicated otherwise, all registers are described in detail in the MSC8101 Reference
Manual, so most of the chapter/section references in the first column of the table are to this manual.
Register
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 6.
Go to: www.freescale.com
HDI16 MSC8101 Register Settings
BCSR0/1
8
15
15
13
4
5–7
0
22–24
27
0
1
10–15
17
19–23
28–31
0
22–24
27
Bits
1
1 1
1 | 0
1
1
011
1
000
0
1
0
000000
1
00000
0101
1
000
1
Setting
Select Host Request mode
Enable HDI16 peripheral. Host address
0x4 is used as host DMA transfer
acknowledge input.
Host Flag 4 on or off
Indicates that an IRQ18 interrupt is
pending. A write clears the interrupt
pending.
IRQ18 – Level triggered
Interrupt Priority Level 3
Internal SRAM address where the next Rx
buffer is to be stored
Size of the Rx buffer
Interrupt on completion
64-bit maximum transfer size
Write transaction
Base size of the buffer
Channel is enabled
Local bus
Buffer Descriptor 0
Flyby mode
HDI16 read request
Priority 5
Internal SRAM address where the next Tx
buffer is to be stored
Size of the Tx buffer
Interrupt on completion
64-bit maximum transfer size
Read transaction
Base size of the buffer
Description