AN2244 Freescale Semiconductor / Motorola, AN2244 Datasheet - Page 22

• Manufacturer Part Number: AN2244
• Description: Interconnecting Two MSC8101ADS Boards Across a 60x-Compatible Bus to the Host Interface
• Manufacturer: Freescale Semiconductor / Motorola

Source Code Files, Software Flow, and Register Settings
22
DMA Channel 0 – BD_ATTR
(0x40000230)
“DMA Programming Model” in the chapter on DMA
DMA Channel 0 – BD_BSIZE
(0x20)
“DMA Programming Model” in the chapter on DMA
DMA Channel 0 – DCHCR
(0x40C00046 | 0xC0C00046)
“DMA Programming Model” in the chapter on DMA
DMA Channel 1 – BD_ADDR
(0x30000020)
“DMA Programming Model” in the chapter on DMA
DMA Channel 1 – BD_SIZE
(0x20)
“DMA Programming Model” in the chapter on DMA
DMA Channel 1 – BD_ATTR
(0x48000220)
“DMA Programming Model” in the chapter on DMA
DMA Channel 1 – BD_BSIZE
(0x20)
“DMA Programming Model” in the chapter on DMA
DMA Channel 1 – DCHCR
(0x40C10905 | 0xC0C10905)
“DMA Programming Model” in the chapter on DMA
DMA Channel 2 – BD_ADDR
(0x30000020)
“DMA Programming Model” in the chapter on DMA
DMA Channel 2 – BD_SIZE
(0x20)
“DMA Programming Model” in the chapter on DMA
DMA Channel 2 – BD_ATTR
(0x48000230)
“DMA Programming Model” in the chapter on DMA
Register
Freescale Semiconductor, Inc.
Table 7. Host MSC8101 Register Settings (Continued)
For More Information On This Product,
Go to: www.freescale.com
0
1
2
4
22–24
26
27
0
1
10–15
17
25
28–31
0
1
2
4
22–24
26
27
0
1
8
9
10–15
17
19–23
25
28–31
0
1
2
4
22–24
26
27
Bits
0
1
0
0
100
1
1
0 | 1
1
000000
0
1
0110
0
1
0
1
100
1
0
0 | 1
1
1
1
000001
0
01001
0
0101
0
1
0
1
100
1
1
Setting
No interrupt
Cyclic address
No continuous buffer
Increment address
32-byte maximum transfer size
Flush FIFO
Read transaction
Size of the Tx buffer
Channel enabled or disabled
60x-compatible bus
Buffer Descriptor 0
Dual access transaction
Internal requestor
Priority 6
Address of memory-mapped HDI16
host-side data registers
Size of the Tx buffer
No interrupt
Cyclic address
No continuous buffer
No address Increment
32-byte maximum transfer size
Flush FIFO
Write transaction
Size of the Tx buffer
Channel enabled or disabled
60x-compatible bus
DREQ level triggered
DREQ active low
Buffer Descriptor 1
Dual access transaction
External request DREQ 2
No internal requestor
Priority 5
Address of memory-mapped HDI16
host-side data registers
Size of the Rx buffer
No interrupt
Cyclic address
No continuous buffer
No address increment
32-byte maximum transfer size
Flush FIFO
Read transaction
Description