AN2244 Freescale Semiconductor / Motorola, AN2244 Datasheet - Page 8

• Manufacturer Part Number: AN2244
• Description: Interconnecting Two MSC8101ADS Boards Across a 60x-Compatible Bus to the Host Interface
• Manufacturer: Freescale Semiconductor / Motorola

HDI16 Device Configuration, Synchronization, and Set-Up
3.1 Device Synchronization
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1
2
3
4
5
6
7
8
Destination
32 Bytes
32 Bytes
SDRAM
Figure 3. DMA Transfer Interaction Between the Host MSC8101 and the HDI16 MSC8101 Devices
Source
An Rx FIFO empty (HTRQ) write request is issued.
DREQ2 assertion: DMA write request triggers transfer.
When 32 bytes are in the FIFO and DREQ2 is asserted, the DMA controller transfers data to the 60x system bus.
An HDI16 write triggers a DMA transfer to memory.
When a 32-byte buffer is full, an interrupt triggers a DMA transfer to a Tx register.
A Tx FIFO not empty (HRRQ) DMA read request is issued.
DREQ1 assertion: a DMA read request triggers a transfer.
When a byte is in the FIFO, the DMA transfers data to SDRAM.
MSC8101 Aggregator
Destination
8
32 Bytes
To synchronize the host and HDI16 software communications, we use host flags to monitor the status of
the communications. We can access eight HDI16 Host Flags (HF) by polling from the host and HDI16
devices. Either the SC140 core or the host can set or clear these “general-purpose flags” for
HDI16-to-host communications. If any of
may indicate an application-specific state within the HDI16 or host requiring intervention by the host
processor or the HDI16 processor. The values of
• For the HDI16 SC140 core side, in the Host Control (HCR) and Host Status (HSR) registers
• For the host side, in the Interface Control (ICR) and in the Interface Status (ISR) registers
For example, if the HDI16 MSC8101 software modifies these HF values, the host MSC8101 can read the
modified values by reading the ISR.
HDI16-to-host communication protocol, implemented in both the HDI16 MSC8101 software and host
2
Channel 1
Channel 2
DMA FIFOs
32 Bytes
32 Bytes
Freescale Semiconductor, Inc.
For More Information On This Product,
32 Bytes
32 Bytes
Source
Go to: www.freescale.com
7
HF[0–7]
6
HF[0–7]
3
can be used individually or as encoded pairs in a simple
HF[0–3]
is set, depending on how the host flags are used, this
1
and
HF[4–7]
HDI16
Rx Register
Tx Register
Rx FIFO
Tx FIFO
HDI16 (DSP-Side) MSC8101
are reflected as follows:
5
4
Internal
SDRAM
32 Bytes
Source