IDT72420L25TP IDT, Integrated Device Technology Inc, IDT72420L25TP Datasheet - Page 5

• Manufacturer Part Number: IDT72420L25TP
• Description: IC FIFO 64X8 SYNC 25NS 28DIP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72420L25TP

• Function: Synchronous
• Memory Size: 512 (64 x 8)
• Data Rate: 67MHz
• Access Time: 25ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 28-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72420L25TP

SIGNAL DESCRIPTIONS
INPUTS:
Data In (D
CONTROLS:
RESET (RS) — Reset is accomplished whenever the Reset (RS) input is
taken to a LOW state. During reset, both internal read and write pointers are
set to the first location. A reset is required after power up before a write
operation can take place. The Full Flag (FF) and Almost-Full Flag (AF) will
be reset to HIGH after t
(AE) will be reset to LOW after t
initialized to all zeros.
WRITE CLOCK (WCLK) — A write cycle is initiated on the LOW-to-HIGH
transition of the Write Clock (WCLK). Data setup and hold times must be met
in respect to the LOW-to-HIGH transition of the Write Clock. The Full Flag
(FF) and Almost-Full Flag (AF) are synchronized with respect to the LOW-
to-HIGH transition of the Write Clock.
WRITE ENABLE (WEN) — When Write Enable (WEN) is LOW, data can
be loaded into the input register and RAM array on the LOW-to-HIGH
transition of every Write Clock (WCLK). Data is stored in the RAM array
sequentially and independently of any on-going read operation.
data and no new data is allowed to be loaded into the register.
further write operations. Upon the completion of a valid read cycle, the Full
Flag (FF) will go HIGH after t
Enable (WEN) is ignored when the FIFO is full.
READ CLOCK (RCLK) — Data can be read on the outputs on the LOW-to-
HIGH transition of the Read Clock (RCLK). The Empty Flag (EF) and
Almost-Empty flag (AE) are synchronized with respect to the LOW-to-HIGH
transition of the Read Clock.
READ ENABLE (REN) — When Read Enable (REN) is LOW, data is read
from the RAM array to the output register on the LOW-to-HIGH transition of
the Read Clock (RCLK).
previous data and no new data is allowed to be loaded into the register.
TABLE 1 — STATUS FLAGS
IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™
64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
The Write and Read Clocks can be asynchronous or coincident.
When Write Enable (WEN) is HIGH, the input register holds the previous
To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting
The Write and Read Clocks can be asynchronous or coincident.
When Read Enable (REN) is HIGH, the output register holds the
IDT72420
57 to 63
8 to 56
1 to 7
64
0
0
–D
7
) — Data inputs for 8-bit wide data.
249 to 255
IDT72200
8 to 248
RSF
1 to 7
256
0
. The Empty Flag (EF) and Almost-Empty Flag
WFF
RSF
, allowing a valid write to begin. Write
. During reset, the output register is
505 to 511
IDT72210
Number of Words in FIFO
8 to 504
1 to 7
512
0
1,017 to 1,023
IDT72220
8 to 1,016
1 to 7
1,024
0
2,041 to 2,047
IDT72230
8 to 2,040
1 to 7
2,048
5
0
go LOW, inhibiting further read operations. Once a valid write operation has
been accomplished, the Empty Flag (EF) will go HIGH after t
read can begin. Read Enable (REN) is ignored when the FIFO is empty.
OUTPUT ENABLE (OE) — When Output Enable (OE) is enabled (LOW),
the parallel output buffers receive data from the output register. When
Output Enable (OE) is disabled (HIGH), the Q output data bus is in a high-
impedance state.
OUTPUTS:
FULL FLAG (FF) — The Full Flag (FF) will go LOW, inhibiting further write
operation, when the device is full. If no reads are performed after Reset
(RS), the Full Flag (FF) will go LOW after 64 writes for the IDT72420, 256
writes for the IDT72200, 512 writes for the IDT72210, 1,024 writes for the
IDT72220, 2,048 writes for the IDT72230, and 4,096 writes for the IDT72240.
transition of the Write Clock (WCLK).
EMPTY FLAG (EF) — The Empty Flag (EF) will go LOW, inhibiting further
read operations, when the read pointer is equal to the write pointer,
indicating the device is empty.
transition of the Read Clock (RCLK).
ALMOST-FULL FLAG (AF) — The Almost-Full Flag (AF) will go LOW when
the FIFO reaches the almost-full condition. If no reads are performed after
Reset (RS), the Almost-Full Flag (AF) will go LOW after 57 writes for the
IDT72420, 249 writes for the IDT72200, 505 writes for the IDT72210, 1,017
writes for the IDT72220, 2,041 writes for the IDT72230 and 4,089 writes for
the IDT72240.
HIGH transition of the Write Clock (WCLK).
ALMOST-EMPTY FLAG (AE) — The Almost-Empty Flag (AE) will go LOW
when the FIFO reaches the almost-empty condition. If no reads are
performed after Reset (RS), the Almost-Empty Flag (AE) will go HIGH after
8 writes for the IDT72420, IDT72200, IDT72210, IDT72220, IDT72230 and
IDT72240.
to-HIGH transition of the Read Clock (RCLK).
DATA OUTPUTS (Q
When all the data has been read from the FIFO, the Empty Flag (EF) will
The Full Flag (FF) is synchronized with respect to the LOW-to-HIGH
The Empty Flag (EF) is synchronized with respect to the LOW-to-HIGH
The Almost-Full Flag (AF) is synchronized with respect to the LOW-to-
The Almost-Empty Flag (AE) is synchronized with respect to the LOW-
4,089 to 4,095
IDT72240
8 to 4,088
1 to 7
4,096
0
0
–Q
7
) — Data outputs for 8-bit wide data.
COMMERCIAL TEMPERATURE RANGE
FF
H
H
H
H
L
AF
H
H
H
L
L
JANUARY 8, 2009
AE
H
H
H
L
L
REF
and a valid
EF
H
H
H
H
L