IDT72241L10J IDT, Integrated Device Technology Inc, IDT72241L10J Datasheet - Page 13

• Manufacturer Part Number: IDT72241L10J
• Description: IC FIFO 2048X18 SYNC 10NS 32PLCC
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72241L10J

• Function: Synchronous
• Memory Size: 36.8K (2K x 18)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-PLCC
• Configuration: Dual
• Density: 36Kb
• Access Time (max): 6.5ns
• Word Size: 9b
• Organization: 4Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: PLCC
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 35mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72241L10J

OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION
when the application requirements are for 64/256/512/1,024/2,048/4,096/
8,192 words or less. When these FIFOs are in a Single Device Configuration,
the Read Enable 2 (REN2) control input can be grounded (see Figure 14). In
this configuration, the Write Enable 2/Load (WEN2/LD) pin is set LOW at Reset
so that the pin operates as a control to load and read the programmable flag
offsets.
WIDTH EXPANSION CONFIGURATION
controls signals of multiple devices. A composite flag should be created for each
of the endpoint status flags (EF and FF). The partial status flags (AE and AF)
can be detected from any one device. Figure 15 demonstrates a 18-bit word
width by using two IDT72421/72201/72211/72221/72231/72241/72251s.
Any word width can be attained by adding additional IDT72421/72201/72211/
72221/72231/72241/72251s.
Enable 2 (REN2) control input can be grounded (see Figure 15). In this
©
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
A single IDT72421/72201/72211/72221/72231/72241/72251 may be used
Word width may be increased simply by connecting the corresponding input
When these FIFOs are in a Width Expansion Configuration, the Read
DATA IN (D)
WRITE ENABLE2/LOAD (WEN2/LD)
Figure 14. Block Diagram of Single 64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 Synchronous FIFO
PROGRAMMABLE ALMOST-FULL (PAF)
WRITE ENABLE 2/LOAD (WEN2/LD)
WRITE ENABLE1 (WEN1)
PROGRAMMABLE (PAF)
Figure 15. Block Diagram of 64 x 18, 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18
WRITE CLOCK (WCLK)
FULL FLAG (FF) #2
FULL FLAG (FF) #1
WRITE ENABLE 1 (WEN1)
18
WRITE CLOCK (WCLK)
READ ENABLE 2 (REN2)
DATA IN (D
Synchronous FIFO Used in a Width Expansion Configuration
FULL FLAG (FF)
9
RESET (RS)
0
- D
72421
72201
72211
72221
72231
72241
72251
IDT
8
)
9
72421
72201
72211
72221
72231
72241
72251
13
IDT
configuration, the Write Enable 2/Load (WEN2/LD) pin is set LOW at Reset so
that the pin operates as a control to load and read the programmable flag offsets.
DEPTH EXPANSION - The IDT72421/72201/72211/72221/72231/72241/
72251 can be adapted to applications when the requirements are for greater
than 64/256/512/1,024/2,048/4,096/8,192 words. The existence of two
enable pins on the read and write port allow depth expansion. The Write
Enable 2/Load pin is used as a second write enable in a depth expansion
configuration thus the Programmable flags are set to the default values. Depth
expansion is possible by using one enable input for system control while the
other enable input is controlled by expansion logic to direct the flow of data. A
typical application would have the expansion logic alternate data access from
one device to the next in a sequential manner. These devices operate in the
Depth Expansion configuration when the following conditions are met:
1. The WEN2/ LD pin is held HIGH during Reset so that this pin operates a
2. External logic is used to control the flow of data.
CHRONOUS FIFOs USING THE RING COUNTER APPROACH" for details
of this configuration.
9
READ ENABLE 2 (REN2)
RESET (RS)
Please see the Application Note "DEPTH EXPANSION OF IDT'S SYN-
READ ENABLE 2 (REN2)
second Write Enable.
RESET (RS)
READ CLOCK (RCLK)
READ ENABLE 1 (REN1)
OUTPUT ENABLE (OE)
DATA OUT (Q
EMPTY FLAG (EF)
PROGRAMMABLE ALMOST-EMPTY (PAE)
72421
72201
72211
72221
72231
72241
72251
IDT
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAE)
EMPTY FLAG (EF) #1
EMPTY FLAG (EF) #2
9
0
- Q
DATA OUT (Q)
8
)
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008
18
2655 drw 17
2655 drw 16