IDT72V251L15J IDT, Integrated Device Technology Inc, IDT72V251L15J Datasheet - Page 13
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IDT72V251L15J
Manufacturer Part Number
IDT72V251L15J
Description
IC FIFO SYNC 4096X18 15NS 32PLCC
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V221L15PFG.pdf
(14 pages)
Specifications of IDT72V251L15J
Function
Synchronous
Memory Size
72K (4K x 18)
Data Rate
67MHz
Access Time
15ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
32-PLCC
Configuration
Dual
Density
72Kb
Access Time (max)
10ns
Word Size
9b
Organization
8Kx9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
PLCC
Clock Freq (max)
66.7MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Supply Current
20mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
32
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V251L15J
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72V251L15J
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V251L15J8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V251L15JI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V251L15JI8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION
used when the application requirements are for 256/512/1,024/2,048/4,096/
8,192 words or less. When these FIFOs are in a Single Device Configuration,
WIDTH EXPANSION CONFIGURATION
controls signals of multiple devices. A composite flag should be created for each
of the end-point status flags (EF and FF). The partial status flags (AE and AF)
can be detected from any one device. Figure 15 demonstrates a 18-bit word
width by using two IDT72V201/72V211/72V221/72V231/72V241/72V251s.
Any word width can be attained by adding additional IDT72V201/72V211/
72V221/72V231/72V241/72V251s.
Enable 2 (REN2) control input can be grounded (see Figure 15). In this
configuration, the Write Enable 2/Load (WEN2/LD) pin is set LOW at Reset so
that the pin operates as a control to load and read the programmable flag offsets.
DEPTH EXPANSION
adapted to applications when the requirements are for greater than 256/512/
IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
A single IDT72V201/72V211/72V221/72V231/72V241/72V251 may be
Word width may be increased simply by connecting the corresponding input
When these devices are in a Width Expansion Configuration, the Read
The IDT72V201/72V211/72V221/72V231/72V241/72V251 can be
DATA IN (D)
WRITE ENABLE2/LOAD (WEN2/LD)
Figure 14. Block Diagram of Single 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 Synchronous FIFO
PROGRAMMABLE ALMOST-FULL (PAF)
WRITE ENABLE 2/LOAD (WEN2/LD)
WRITE ENABLE1 (WEN1)
PROGRAMMABLE (PAF)
Figure 15. Block Diagram of 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 and 8,192 x 18
WRITE CLOCK (WCLK)
WRITE ENABLE 1 (WEN1)
FULL FLAG (FF) #2
FULL FLAG (FF) #1
WRITE CLOCK (WCLK)
18
DATA IN (D
FULL FLAG (FF)
READ ENABLE 2 (REN2)
Synchronous FIFO Used in a Width Expansion Configuration
9
0
- D
RESET (RS)
72V201
72V211
72V221
72V231
72V241
72V251
8
)
IDT
9
72V201
72V211
72V221
72V231
72V241
72V251
13
IDT
the Read Enable 2 (REN2) control input can be grounded (see Figure 14). In
this configuration, the Write Enable 2/Load (WEN2/LD) pin is set LOW at Reset
so that the pin operates as a control to load and read the programmable flag
offsets.
1,024/2,048/4,096/8,192 words. The existence of two enable pins on the read
and write port allow depth expansion. The Write Enable 2/Load pin is used as
a second write enable in a depth expansion configuration thus the program-
mable flags are set to the default values. Depth expansion is possible by using
one enable input for system control while the other enable input is controlled by
expansion logic to direct the flow of data. A typical application would have the
expansion logic alternate data access from one device to the next in a sequential
manner. These FIFOs operate in the Depth Expansion configuration when the
following conditions are met:
1. The WEN2/ LD pin is held HIGH during Reset so that this pin
2. External logic is used to control the flow of data.
CHRONOUS FIFOs USING THE RING COUNTER APPROACH" for details
of this configuration.
RESET (RS)
READ ENABLE 2 (REN2)
Please see the Application Note" DEPTH EXPANSION OF IDT'S SYN-
9
READ ENABLE 2 (REN2)
operates a second Write Enable.
RESET (RS)
72V201
72V211
72V221
72V231
72V241
72V251
READ CLOCK (RCLK)
READ ENABLE 1 (REN1)
OUTPUT ENABLE (OE)
DATA OUT (Q
EMPTY FLAG (EF)
PROGRAMMABLE ALMOST-EMPTY ( PAE)
IDT
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAE)
EMPTY FLAG (EF) #1
EMPTY FLAG (EF) #2
0
9
- Q
8
DATA OUT (Q)
)
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008
18
4092 drw16
4092 drw17