IDT72261LA20PF IDT, Integrated Device Technology Inc, IDT72261LA20PF Datasheet
IDT72261LA20PF
Specifications of IDT72261LA20PF
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IDT72261LA20PF Summary of contents
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FEATURES: • • • • • Choose among the following memory organizations: IDT72261LA 16,384 x 9 IDT72271LA 32,768 x 9 • • • • • Pin-compatible with the IDT72281/72291 SuperSync FIFOs • • • • • 10ns read/write cycle time ...
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IDT72261LA/72271LA SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 DESCRIPTION (CONTINUED) SuperSync FIFOs are particularly appropriate for network, video, telecom- munications, data communications and other applications that need to buffer large amounts of data. The input port is controlled ...
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IDT72261LA/72271LA SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 DESCRIPTION (CONTINUED) In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. A REN ...
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IDT72261LA/72271LA SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 PIN DESCRIPTION Symbol Name D –D Data Inputs 0 8 MRS Master Reset PRS Partial Reset RT Retransmit FWFT/SI First Word Fall WCLK Write Clock WEN Write Enable RCLK Read ...
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IDT72261LA/72271LA SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with respect to GND T Storage STG Temperature I DC Output Current OUT NOTE: 1. Stresses greater than those listed under ...
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IDT72261LA/72271LA SuperSync FIFO™ 16,384 x 9 and 32,768 ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5V ± 10 0°C to +70°C; Industrial: VCC = 5V ± 10 –40°C to +85°C) Symbol Parameter f Clock Cycle ...
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IDT72261LA/72271LA SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 FUNCTIONAL DESCRIPTION TIMING MODES: IDT STANDARD VS FIRST WORD FALL THROUGH (FWFT) MODE The IDT72261LA/72271LA support two different timing modes of opera- tion: IDT Standard mode or First Word Fall ...
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IDT72261LA/72271LA SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 PROGRAMMING FLAG OFFSETS Full and Empty Flag offset values are user programmable. The IDT72261LA/72271LA has internal registers for these offsets. Default settings are stated in the footnotes of Table 1 ...
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IDT72261LA/72271LA SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 IDT72261LA ⎯ 16,384 x 9 ⎯ BIT 8 7 EMPTY OFFSET (LSB) REG. 07FH LOW at Master Reset 3FFH HIGH at Master Reset 8 ...
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IDT72261LA/72271LA SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 SERIAL PROGRAMMING MODE If Serial Programming mode has been selected, as described above, then programming of PAE and PAF values can be achieved by using a combination of the LD, ...
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IDT72261LA/72271LA SuperSync FIFO™ 16,384 x 9 and 32,768 FWFT mode is selected, the FIFO will mark the beginning of the Retransmit setup by setting OR HIGH. During this period, the internal read pointer is set to the ...
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IDT72261LA/72271LA SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 SIGNAL DESCRIPTION INPUTS: DATA IN (D0 - D8) Data inputs for 9-bit wide data. CONTROLS: MASTER RESET (MRS) A Master Reset is accomplished whenever the MRS input is taken to ...
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IDT72261LA/72271LA SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 WRITE ENABLE (WEN) When the WEN input is LOW, data may be loaded into the FIFO RAM array on the rising edge of every WCLK cycle if the device is ...
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IDT72261LA/72271LA SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 valid on the outputs. OR stays LOW after the RCLK LOW to HIGH transition that shifts the last word from the FIFO memory to the outputs. OR goes HIGH only ...
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IDT72261LA/72271LA SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 MRS REN WEN t FWFT FWFT/ SEN EF/OR FF/IR PAE PAF RSS t t RSS ...
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IDT72261LA/72271LA SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 PRS REN WEN RT SEN EF/OR FF/IR PAE PAF RSS t RSS t RSS t RSS t RSF t RSF t ...
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IDT72261LA/72271LA SuperSync FIFO™ 16,384 x 9 and 32,768 WRITE WCLK 1 (1) t SKEW1 WEN RCLK t t ENS ENH REN DATA IN OUTPUT REGISTER ...
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IDT72261LA/72271LA SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 COMMERCIAL AND INDUSTRIAL 18 TEMPERATURE RANGES JANUARY 7, 2009 ...
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IDT72261LA/72271LA SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 COMMERCIAL AND INDUSTRIAL 19 TEMPERATURE RANGES JANUARY 7, 2009 ...
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IDT72261LA/72271LA SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 RCLK t t ENS ENH t RTS REN WCLK t WEN t ENS RT EF PAE HF PAF NOTES: 1. Retransmit ...
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IDT72261LA/72271LA SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 RCLK t t ENH ENS t RTS REN WCLK t RTS WEN t ENS RT OR PAE HF PAF NOTES: 1. Retransmit setup ...
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IDT72261LA/72271LA SuperSync FIFO™ 16,384 x 9 and 32,768 CLK t t CLKH CLKL WCLK t LDS LD t ENS WEN PAE OFFSET (LSB) Figure 14. Parallel Loading of Programmable Flag ...
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IDT72261LA/72271LA SuperSync FIFO™ 16,384 x 9 and 32,768 CLKH CLKL WCLK t t ENH ENS WEN (2) n words in FIFO PAE , (3) n+1 words in FIFO (4) t SKEW2 RCLK 1 REN NOTES: 1. ...
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IDT72261LA/72271LA SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 OPTIONAL CONFIGURATIONS WIDTH EXPANSION CONFIGURATION Word width may be increased simply by connecting together the control signals of multiple devices. Status flags can be detected from any one device. The ...
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IDT72261LA/72271LA SuperSync FIFO™ 16,384 x 9 and 32,768 x 9 DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY) The IDT72261LA can easily be adapted to applications requiring depths greater than 16,384 and 32,768 for the IDT72271LA with a 9-bit bus width. In ...
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ORDERING INFORMATION XXXXX X XX Device Type Power Speed NOTES: 1. Industrial temperature range product for 15ns and 20ns speed grade are available as a standard device. 2. Green parts available. For specific speeds and packages contact your sales office. ...
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VOLT CMOS SuperSync FIFO 16,384 x 9 32,768 x9 DIFFERENCES BETWEEN THE IDT72261LA/72271LA AND IDT72261L/72271L IDT has improved the performance of the IDT72261/72271 SuperSync™ FIFOs. The new versions are designated by the “LA” mark. The LA part is pin-for-pin ...