IDT72V261LA15TFI IDT, Integrated Device Technology Inc, IDT72V261LA15TFI Datasheet - Page 21
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IDT72V261LA15TFI
Manufacturer Part Number
IDT72V261LA15TFI
Description
IC FIFO SS 8192X18 15NS 64QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V271LA10PFG.pdf
(27 pages)
Specifications of IDT72V261LA15TFI
Function
Synchronous
Memory Size
144K (8K x 18)
Data Rate
67MHz
Access Time
15ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-STQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V261LA15TFI
NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
3. OE = LOW.
4. W
5. OR goes LOW at 60 ns + 2 RCLK cycles + t
NOTE:
1. X = 13 for the IDT72V261LA and X = 14 for the IDT72V271LA.
Q
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
WCLK
WCLK
RCLK
0
D = 16,385 for the IDT72V261LA and 32,769 for the IDT72V271LA.
WEN
SEN
PAE
REN
PAF
- Q
1
LD
OR
, W
HF
RT
SI
n
2
, W
t
ENS
3
= first, second and third words written to the FIFO after Master Reset.
W
x
t
Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
ENH
BIT 0
t
t
t
ENS
LDS
DS
t
ENS
t
RTS
t
RTS
REF
.
t
t
ENH
LDH
EMPTY OFFSET
t
t
REF
t
ENH
HF
t
SKEW4
1
Figure 12. Retransmit Timing (FWFT Mode)
2
t
PAF
1
W
x+1
BIT X
21
(1)
BIT 0
2
t
PAE
FULL OFFSET
COMMERCIAL AND INDUSTRIAL
3
t
A
t
ENH
t
REF
TEMPERATURE RANGES
(5)
W
1
(4)
BIT X
t
t
t
JANUARY 30, 2009
LDH
LDH
ENH
t
DH
(1)
W
4
2
t
A
4673 drw 16
t
ENH
4673 drw15
W
3