IDT72615L20J8 IDT, Integrated Device Technology Inc, IDT72615L20J8 Datasheet - Page 16

• Manufacturer Part Number: IDT72615L20J8
• Description: IC FIFO BY SYNC 512X18X2 68PLCC
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72615L20J8

• Function: Synchronous
• Memory Size: 18.4K (512 x 18 x 2)
• Data Rate: 50MHz
• Access Time: 20ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72615L20J8

NOTES:
1. t
2. If a read is performed on this rising edge of the read clock, there will be Empty + (n - 1) words in the FIFO when PAE goes LOW.
NOTES:
1. t
2. If a write is performed on this rising edge of the write clock, there will be Full - (m + 1) words in the FIFO when PAF goes LOW.
IDT72605/72615 CMOS SYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2
(R/W
(R/W
(R/W
(R/W
and the rising edge of CLK
and the rising edge of CLK
SKEW2
SKEW2
PAE
PAF
A
A
A
A
CLK
CLK
CLK
CLK
EN
EN
EN
EN
= 0)
= 1)
= 0)
= 1)
is the minimum time between a rising CLK
is the minimum time between a rising CLK
BA
BA
B
B
A
A
B
B
A
A
t
t
CLKH
CLKH
A
A
is less than t
is less than t
n words in FIFO
t
SKEW2
Full - (m+1) words in FIFO
t
t
CS
CS
t
t
CLKL
CLKL
(1)
WRITE
WRITE
SKEW2
SKEW2
, then PAE
, then PAF
Figure 14. B → → → → → A Programmable Almost-Empty Flag Timing
Figure 15. B → → → → → A Programmable Almost-Full Flag Timing
B
B
t
t
CH
edge and a rising CLK
edge and a rising CLK
CH
t
BA
BA
PAE
may not go HIGH until the next CLK
may not go HIGH until the next CLK
(2)
A
A
t
edge for PAE
edge for PAF
PAF
16
BA
BA
to change during that clock cycle. If the time between the rising edge of CLK
to change during that clock cycle. If the time between the rising edge of CLK
t
CS
A
A
n+1 words in FIFO
rising edge.
rising edge.
Full - m words in FIFO
READ
t
SKEW2
t
CS
t
CH
(1)
READ
INDUSTRIAL TEMPERATURE RANGE
t
CH
(2)
t
PAF
t
PAE
2704 drw 17
2704 drw 18
B
B