SPC8110F0A EPSON Research and Development, Inc., SPC8110F0A Datasheet
SPC8110F0A
Related parts for SPC8110F0A
SPC8110F0A Summary of contents
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... SPC8110F0A LOCAL BUS LCD/CRT VGA CONTROLLER DESCRIPTION The SPC8110 is a single chip, multi-function, mixed voltage LCD/CRT VGA controller. This controller features an integrated RAMDAC, PLL, Bit Block Transfer engine (BitBLT) and a CPU local bus interface. The SPC8110 accelerates the display of graphical user interface software on flat panel and analog CRT displays ...
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... Shown with 1024 KB memory option PCI BUS PAR AD[31:0] C/BE[3:0]# FRAME# IRDY# TRDY# DEVSEL# STOP# IDSEL RST# CLK 14.318MHz 2 Power RTC Management 32kHz PAR AD[31:0] C/BE[3:0]# SPC8110F0A FRAME# IRDY# TRDY# DEVSEL# STOP# IDSEL RESET# BCLK REFCLK 256Kx16DRAM 256Kx16DRAM IREF IREF BLUE BLUE GREEN GREEN CRT RED RED VSYNC VSYNC ...
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... X07-DS-001-21 Power RTC Management 32kHz ADR[31:2] DAT[31:0] SPC8110F0A BE[3:0]# ADS# RDYRTN# LRDY# LDEV# M/IO# W/R# BCLK RESET# REFCLK 256Kx16 DRAM 256Kx16 DRAM GRAPHICS SPC8110F0A IREF IREF BLUE BLUE GREEN GREEN CRT RED RED VSYNC VSYNC HSYNC HSYNC MONID[2:0] UD[7:0] UD[7:0] LD[7:0] LD[7:0] XSCL XSCL 16-bit XSCLU ...
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... LOCAL BUS ADR[31:2] DAT[31:0] BE[3:0]# ADS# RDY# M/IO# W/R# CLK RESET# 486 Chipset LDEV# 14.318MHz 4 Power RTC Management 32kHz ADR[31:2] DAT[31:0] BE[3:0]# ADS# SPC8110F0A RDYRTN# LRDY# M/IO# W/R# BCLK RESET# LDEV# REFCLK 256Kx16 DRAM IREF IREF BLUE BLUE GREEN GREEN CRT RED RED VSYNC VSYNC HSYNC HSYNC ...
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... GRAPHICS SPC8110F0A Nominal Frame Rate Number of Shades (Hz) for 1024KB RAM Single Dual Mono Color CRT CRT Panel Panel LCD LCD (typical) LCD LCD ...
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... GRAPHICS SPC8110F0A FUNCTIONAL BLOCK DIAGRAM 14.318MHz ADR[31:2] Host DAT[31:0] I/F BUS CONTROL H/W Cursor MA[9:0] MDA[15:0] MDB[15:0] RAS# CAS[3:0]# WE# PS1PIN PS4PIN 32KHz 6 Clock Generation VGA Palette Core Display BitBLT Engine FIFO LCD DRAM Controller Controller I/F Power Down Circuit Red Green Blue HSYNC VSYNC DAC ...
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... GRAPHICS SPC8110F0A FUNCTIONAL BLOCK DESCRIPTION Host Interface The Host Interface can be programmed to accommodate any of the following three stan- dards: Intel486 DX local bus interface, VL-Bus interface and PCI interface. It has a one-stage buffer for zero wait-state write operation. Clock Generator The Clock Generator contains two PLLs that are separately programmed to produce the memory and pixel clocks from a single clock source ...
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... GRAPHICS SPC8110F0A ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Symbol Parameter V Supply Voltage DD V Input Voltage IN V Output Voltage OUT T Storage Temperature STG T Solder Temperature/Time SOL Recommended Operating Conditions Symbol Parameter HV Supply Voltage DD LV Supply Voltage DD V Input Voltage IN T Operating Temperature OPR ...
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... Min Typ V = 5/3. 6mA 12mA 24mA 5/3. -2mA 0 -4mA -8mA MAX GRAPHICS SPC8110F0A Max Units -- 0 100 K 90 180 K 2 Max Units ...
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... RST# 203 ADR10 204 ADR11 205 ADR12 206 ADR13 207 BCLK 208 BVSS Note: Pin names correspond to the PCI bus configuration. Pin placement subject to change. 10 AVDD SPC8110F0A BVDD 104 MVSS 103 MDA10 102 MDA5 101 MDA11 100 MDA4 99 MDA12 98 MDA3 97 MDA13 ...
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... PCI Bus Target Ready. PCI Bus Device Select. CPU Reset. The active low reset signal from the CPU clears all internal registers and forces all signals to their inactive state. On the rising edge of the RESET# the MDA[0...15] bus is latched in for configuration. GRAPHICS SPC8110F0A 11 ...
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... GRAPHICS SPC8110F0A Intel486/VL-Bus Output Pin Name Type Pin No. Type 20-3, 206-203, ADR[31: 200-193 22-29, 34-41, 51, DAT[31:0] I/O 4 55-61, 65-72 BE[3:0 30, 43, 50 M/IO ADS RDYRTN BCLK I -- 207 LRDY LDEV RESET# -- 202 w/SCH PAR Description VL-Bus Address inputs. These inputs are unused and must be tied high in PCI Bus mode ...
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... REFCLK may shut down only after the chip is totally powered down. Input frequency is typically 14.318 MHz. Real Time Clock. This input must be used to provide a low frequency 153 clock for generating DRAM refresh. This clock must be approximately 32 kHz and 50% duty cycle. GRAPHICS SPC8110F0A 13 ...
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... GRAPHICS SPC8110F0A CRT INTERFACE Output Pin Name Type Pin No. Description Type RED, GREEN, 140 BLUE 138, 136 HSYNC O 3 149 VSYNC O 3 152 IREF AI -- 142 MONID[2: 147-145 Monitor ID bits. Connected to the CRT to identify the monitor type. LCD PANEL INTERFACE FPDI-1 PIN ...
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... PVSS P 181 X07-DS-001-21 Pin No. Description This pin, when high, sets the SPC8110F0A into either boundary pin SCAN or pin output drive test, depending on the state of PS1PIN. 148 This input has an internal pull down resistor that has a typical value of 50K/100K at 5 V/3.3 V respectively. ...
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... GRAPHICS SPC8110F0A Pin Name Type Pin No. AGND P 133, 144 MCLVSS P 123, 172 INTEL486/VL-BUS TO PCI BUS PIN MAPPING VL-Bus Name PCI Name RESET# RST# RDYRTN# IRDY# ADR[31:2] -- W/R# IDSEL LDEV# DEVSEL# DAT[31:0] AD[31:0] MIXED VOLTAGE OPERATION SOGVDD, Mixed Voltage MCLVDD, AVDD Configuration 1 Configuration 2 ...
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... G2 UD7 UD7 UD0 UD0 UD1 UD1 B0 UD2 UD2 B1 B0 UD3 UD3 (DISP) (DISP) GRAPHICS SPC8110F0A Mono LCD 8-Bit 6-Bit 8-Bit 4-Bit XSCLU XSCL XSCL XSCL XSCL UD0 UD0 UD1 UD1 UD2 UD2 UD3 ...
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... GRAPHICS SPC8110F0A ALTERNATE PIN MAPPING FOR THE VARIOUS LCD AND TFT PANEL OPTIONS TFT Pin Name 18-Bit 9-Bit x 2 Color Color XSCLU CLK CLK XSCL LD4 R0 R10 LD5 R1 R11 LD6 R2 R12 LD7 R3 R00 LD0 R4 R01 LD1 R5 R02 LD2 ...
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... tim VDP = Vertical Display Period VNDP = Vertical Non-Display Period HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period X07-DS-001-21 VDP LIN E239 HDP 1-5 1-6 1-7 1-8 GRAPHICS SPC8110F0A VNDP LIN E240 HNDP 1-317 1-318 1-319 1-320 19 ...
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... GRAPHICS SPC8110F0A MONOCHROME PASSIVE STN LCD PANEL INTERFACE 8-Bit Single Panel UD[3:0], LD[3: XSCL UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0 * diagram drawn with 2 LP vertical blank period example timing for 640x480 panel VDP = Vertical Display Period VNDP = Vertical Non-Display Period ...
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... HNDP = Horizontal Non-Display Period X07-DS-001-21 VDP LINE 1/241 LINE 2/242 LINE 3/243 LINE4/244 LINE 239/479 LINE240/480 HDP 1 1-1 -5 1-2 1-6 1-3 1-7 1-4 1-8 241-1 241-5 241-2 241-6 241-3 241-7 241-4 241-8 GRAPHICS SPC8110F0A VNDP LINE 1/241 LIN E 2/242 HNDP 1-637 1-638 1-639 1-640 241-637 241-638 241-639 241-640 21 ...
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... GRAPHICS SPC8110F0A COLOR PASSIVE STN LCD PANEL INTERFACE 6-Bit Dual Color Panel UD[2:0], LD[2:0] LP ENAB (WF) XSCL UD2 UD1 UD0 LD2 LD1 LD0 * diagram drawn with 2 LP vertical blank period example timing for 640x480 panel VDP = Vertical Display Period VNDP = Vertical Non-Display Period ...
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... LINE4 LINE479 LINE480 HDP HDP 1-R1 1-G1 1-G6 1-B6 1-B11 1-R12 1 1-B1 1-R2 1-R7 1-G7 -G12 1-B12 1 1-G2 1-B2 1-B7 1-R8 -R13 1-G13 1-R3 1-G3 1-G8 1-B8 1-B13 1-R14 1 1-B3 1-R4 1-R9 1-G9 -G14 1-B14 1 1-G4 1-B4 1-B9 1-R10 -R15 1-G15 1 1-R5 1-G5 1-G10 1-B10 -B15 1-R16 1 1-B5 1-R6 1-R11 1-G11 -G16 1-B16 GRAPHICS SPC8110F0A VNDP LINE1 LINE2 HNDP HNDP 1-R636 1-B636 1-G637 1-R638 1-B638 1-G639 1-R640 1-B640 23 ...
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... GRAPHICS SPC8110F0A COLOR PASSIVE STN LCD PANEL INTERFACE 8-Bit Single Color Panel (Alternate Data Format UD[3:0], LD[3: XSCL UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0 * diagram drawn with 2 LD vertical blank period Example timing for a 640 x 480 panel VDP = Vertical Display Period ...
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... GRAPHICS SPC8110F0A VNDP LIN E1/241 HNDP 1-B639 1-R640 1-G640 1-B640 241- B639 241- R640 241- G640 241- B640 25 ...
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... GRAPHICS SPC8110F0A COLOR PASSIVE STN LCD PANEL INTERFACE 8-Bit Dual Color Panel (Two Shift Clocks UD[3:0], LD[3: XSCLU XSCL UD3 UD2 UD1 UD0 LD3 LD2 241-G1 LD1 LD0 * diagram drawn with 2 LP vertical blank period example timing for 640x480 panel VDP = Vertical Display Period ...
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... GRAPHICS SPC8110F0A VNDP LINE1 LINE2 HNDP 1-G635 1-G636 1-R637 1-B637 1-G638 1-R639 1-B639 1-G640 1-R636 1-B636 1-G637 1-R638 1-B638 1-G639 1-R640 1-B640 27 ...
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... GRAPHICS SPC8110F0A COLOR PASSIVE STN LCD PANEL INTERFACE 16-Bit Dual Color Panel UD[7:0], LD[7: XSCL UD7, LD7 UD6, LD6 UD5, LD5 UD4, LD4 UD3, LD3 UD2, LD2 UD1, LD1 UD0, LD0 * diagram drawn with 2 LP vertical blank period example timing for 640x480 panel ...
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... Note: DE (Data Enable) is used to indicate the first pixel Example Timing for 640 x 480 panel VPERIOD = Vertical Display Period VDP = Vertical Display Period HPERIOD = Horizontal Period HDP = Horizontal Display Period X07-DS-001-21 GRAPHICS SPC8110F0A VPERIOD VDP LINE1 LINE480 HPERIOD HDP 1-1 1-2 1-640 1-1 ...
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... GRAPHICS SPC8110F0A ACTIVE MATRIX LCD PANEL INTERFACE 2 X 9-Bit Color TFT VS (YD Pin) HS (LP Pin (WF Pin (LP Pin) CLK DE (WF Pin) R0[2:0] G0[2:0] B0[2:0] R1[2:0] G1[2:0] B1[2:0] Note: DE (Data Enable) is used to indicate the first pixel example timing for 1024x768 panel VPERIOD = Vertical Display Period ...
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... LINE 240 LINE 241 LINE 480 LP: 480 PULSES LINE 2 LINE 240 LINE 241 LINE 480 HRTC: 480 P ULSES LINE 2 LINE 240 LINE 241 LINE 480 GRAPHICS SPC8110F0A LP: 45 PULSES LINE 1 LINE 2 LP: 45 PULSES LINE 1 LINE 2 LINE 241 LINE 242 LP: 45 PULSES LINE 1 LINE 2 ...
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... GRAPHICS SPC8110F0A PACKAGE DIMENSIONS QFP8 - 208 S1 156 157 208 1 32 ±0.4 30.6 ±0.1 28.0 Index ±0.1 ±0.1 0.5 0.2 ±0.2 0.5 1.3 Unit: mm 105 104 53 52 0~12° Actual Size X07-DS-001-21 ...
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... CPU Independent Software Utilities • Evaluation Software • Windows CE Display Driver Application Engineering Support Seiko Epson offers the following services through their Sales and Marketing Network: • Sales Technical Support • Customer Training • Design Assistance X07-DS-001-21 GRAPHICS SPC8110F0A 33 ...
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... GRAPHICS SPC8110F0A CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS: • SPC8110 Technical Manual • SDU8110 Evaluation Boards • Windows CE Display Driver • CPU Independent Software Utilities Japan Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan ...