SPC8110F0A EPSON Research and Development, Inc., SPC8110F0A Datasheet - Page 13

• Manufacturer Part Number: SPC8110F0A
• Description: LOCAL BUS LCD/CRT VGA CONTROLLER
• Manufacturer: EPSON Research and Development, Inc.

X07-DS-001-21
Pin Name
MA[9:0]
MDA[15:0]
MDB[15:0]
RAS#
CAS[0]#
(CAS#)
CAS[3:1]#
(WE[3:1]#)
WE#
(WE[0]#)
Pin Name
REFCLK
RTCLK
VIDEO MEMORY INTERFACE
CLOCK INPUTS
Type
O
I/O
w/
PD
I/O
w/
PD
O
O
O
O
Type
I
I
Output
Type
2
2
2
2
2
2
2
Output
Type
--
--
Pin No.
119, 120, 126,
128, 130, 132,
131, 129, 127,
125
93, 95, 97, 99,
101, 103, 108,
110, 109, 107,
102, 100, 98, 96,
94, 92
74, 76, 78, 80,
83, 85, 87, 89,
88, 86, 84, 82,
79, 77, 75, 73
118
113
116-114
117
Pin No.
155
153
Description
Multiplexed row/column address bits for video display memory.
Data bits for video display memory. The output drivers of these pins
are placed into a high-impedance state when RESET# is low, or when
MClkOFF is active. These pins are also used as configuration inputs.
They have internal pull down resistors that have typical values of
50K
Data bits for video display memory when 1024KB of memory is
present. The output drivers of these pins are placed into a high-
impedance state when RESET# is low, or when MClkOFF is active.
The inputs have internal pull down resistors that have typical values
of 50K
open-circuit when only 512KB of memory is attached.
DRAM Row Address Strobe.
DRAM Column Address Strobe for MDA[7:0], or Column Address
Strobe for all bytes, as configured by an auxiliary register.
DRAM Column Address Strobes or Write Enable Strobes for
{MDB[15:0],MDA[15:8]}, as configured by an auxiliary register.
CAS[3:2]# (WE[3:2]#) are unused and should be left open-circuit
when only 512KB of memory is present.
DRAM Write Enable Strobe for all bytes or Write Enable Strobe for
MDA[7:0], as configured by an auxiliary register.
Description
This pin is the reference clock used by the internal PLLs to generate
all the necessary clocks. This must be stable during full operation.
REFCLK may shut down only after the chip is totally powered down.
Input frequency is typically 14.318 MHz.
Real Time Clock. This input must be used to provide a low frequency
clock for generating DRAM refresh. This clock must be
approximately 32 kHz and 50% duty cycle.
at 5V/3.3V respectively.
at 5 V/3.3 V respectively. They should be left
SPC8110F0A
GRAPHICS
13