SPC8110F0A EPSON Research and Development, Inc., SPC8110F0A Datasheet - Page 14

• Manufacturer Part Number: SPC8110F0A
• Description: LOCAL BUS LCD/CRT VGA CONTROLLER
• Manufacturer: EPSON Research and Development, Inc.

Pin Name
RED, GREEN,
BLUE
HSYNC
VSYNC
IREF
MONID[2:0]
Pin Name
YD
LP
XSCL
XSCLU
UD[7:0]
LD[7:0]
TFTB[5:4]
LCDBIAS
LCDBACK
LCDLOGIC
WF
14
SPC8110F0A
CRT INTERFACE
LCD PANEL INTERFACE
1. VESA Flat Panel Display Interface Standard (FPDI-1
GRAPHICS
FPDI-1 PIN
Name
FPFRAME
FPLINE
FPSHIFT
FPSHIFT2
UD[7:0]
LD[7:0]
MOD
Type
AO
O
O
AI
I
-
-
-
-
1
Output
Type
--
3
--
--
3
Type
O
O
I/O
O
O
O
O
O
O
O
Pin No. Description
140,
138, 136
149
152
142
147-145 Monitor ID bits. Connected to the CRT to identify the monitor type.
Output
4
4
4
4
4
4
2
2
2
4
Type
Pin No.
165
164
163
162
180-177,
186-183,
170-167,
176-173
188-187
190
192
191
189
Analog outputs from the Video DAC. Internal comparator for monitor sense is
available on all three pins. This pin should be connected to AGND if the DAC is
not required.
Horizontal Sync. This output is driven to indicate the horizontal retrace period. In
CRT only mode, the polarity of this signal is controlled by register 3C2h, bit 6. In
TFT or double scan mode this bit is active low to indicate 640 x 480 resolution.
This pin is held low in LCD modes. This pin follows the DPMS standard during
power down modes.
Vertical Sync. This output is driven to indicate the vertical retrace period. In CRT
only mode, the polarity of this signal is controlled by register 3C3h, bit 7. In TFT
or double scan mode this bit is active low to indicate 640 x 480 resolution. This
pin is held low in LCD modes. This pin follows the DPMS standard during power
down modes.
Current reference input for the Video DAC. This pin should be connected to
AGND if the DAC is not required. See “External Reference Component Values”
document, X07G-G-002-xx.
Description
Vertical Scanning Start Pulse output. A logic 1 on this signal, sampled
by the LCD module on the falling edge of LP, is used by the panel row
drivers (Y drivers) to indicate the start of the vertical frame.
Latch Pulse output. The falling edge of this signal is used to latch a
row of display data in the LCD module’s column driver shift registers
and to turn on the row driver (Y driver) for that line.
Shift Clock for LCD data. Display data is clocked out of the chip on
the rising edge of this signal, to be shifted into the LCD panel module
column drivers (X drivers) on each falling edge.
Second Shift Clock for some color LCD displays.
Panel display data bus. The data format depends on the specific panel
connected. These pins are driven low when the LCD interface is
disabled (e.g. CRT only mode). For 8-bit panels, UD[7:4] and LD[7:4]
are driven low.
TFT display data bus for the two lsb of the color blue. For non-TFT
panels, these two pins are driven low.
LCD power control for the LCD bias circuitry. Active (On) polarity is
defined by the state of MDA[3] on the rising edge of RESET#.
LCD power control for the LCD back light. Active (On) polarity is
defined by the state of MDA[1] on the rising edge of RESET#.
LCD power control for the LCD logic circuitry. Active (On) polarity is
defined by the state of MDA[2] on the rising edge of RESET#.
LCD Backplane Bias signal. Output toggling frequency is
programmable in an auxiliary register. For TFT panels, this pin
outputs the display enable signals.
TM
)
X07-DS-001-21