SPC8110F0A EPSON Research and Development, Inc., SPC8110F0A Datasheet - Page 7

• Manufacturer Part Number: SPC8110F0A
• Description: LOCAL BUS LCD/CRT VGA CONTROLLER
• Manufacturer: EPSON Research and Development, Inc.

Host Interface
Clock Generator
VGA Core
Hardware Cursor
BitBLT Engine
SPC8110F0A
7
FUNCTIONAL BLOCK DESCRIPTION
The Host Interface can be programmed to
accommodate any of the following three stan-
dards: Intel486 DX local bus interface, VL-Bus
interface and PCI interface. It has a one-stage
buffer for zero wait-state write operation.
The Clock Generator contains two PLLs that are
separately programmed to produce the memory
and pixel clocks from a single clock source. The
reference clock is typically 14.318 MHz.
The VGA Core contains the Sequencer, CRTC
Controller, Graphics Controller, Attribute Con-
troller, and the rest of the standard VGA circuitry.
The Hardware Cursor generates a 64 x 64 x
2-bit hardware cursor or sprite that can be over-
laid on the displayed image.
The Bit Block Transfer Engine performs read,
write, and move blits, solid fills, destination inver-
sions, and pattern fills. It performs all data
alignment and masking at the blit boundary and
also performs color expansion to accelerate the
writing of text images. The Bit Block Transfer
Engine operates in both 4-bit planar mode and
8-bit linear (packed-pixel) mode.
GRAPHICS
Display FIFO
VGA Palette
DAC
LCD Interface
Power Save Logic
The Display FIFO is an 8 stage FIFO that is
used to buffer the video data from display
memory.
The VGA Palette implements the standard 256-
word x 18-bit VGA lookup table, plus 4-word x
18-bit entries for Hardware Sprites.
The DAC functions as a triple 6-bit 65 MHz DAC
to drive the RGB outputs connected to the ana-
log display.
The LCD Interface contains frame rate modula-
tion and dithering circuitry displaying a maxi-
mum of 64 shades of gray in monochrome LCD
mode. In color LCD mode, it uses frame rate
modulation (FRM) to display 256 out of a possi-
ble 4096 colors, and additional dithering tech-
niques for a full 256K possible colors.
Power Save Logic implements all the power
down features of the chip.
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