SPC8110F0A EPSON Research and Development, Inc., SPC8110F0A Datasheet - Page 12

• Manufacturer Part Number: SPC8110F0A
• Description: LOCAL BUS LCD/CRT VGA CONTROLLER
• Manufacturer: EPSON Research and Development, Inc.

Intel486/VL-Bus
Pin Name
ADR[31:2]
DAT[31:0]
BE[3:0]#
W/R#
M/IO#
ADS#
RDYRTN#
BCLK
LRDY#
LDEV#
RESET#
PAR
12
SPC8110F0A
GRAPHICS
I
I
I
O
Type
I
I/O
I
I
I
O
O
I
w/SCH
Output
Type
--
4
--
--
4
--
--
--
4
4
--
4
30, 43, 50, 62
31
Pin No.
20-3, 206-203,
200-193
22-29, 34-41, 51,
55-61,
65-72
48
44
45
207
46
47
202
49
Description
VL-Bus Address inputs. These inputs are unused and must be tied high in
PCI Bus mode.
VL-Bus Data inputs. These lines are driven by the chip only during read
cycles, and are in a hi-Z state at all other times.
VL-Bus byte enables.
VL-Bus Write or Read Status.
VL-Bus Memory or I/O Status.
VL-Bus Ready Return.
VL-Bus Local CPU Clock.
VL-Bus Local Ready.
VL-Bus Local Device.
CPU Reset. The active low reset signal from the CPU clears all internal
registers and forces all signals to their inactive state. On the rising edge of
the RESET# the MDA[0...15] bus is latched in for configuration.
Unused (Parity). This line is used in PCI mode only. It is hi-Z at all times
in VL-Bus mode and should be tied high.
VL-Bus Address Data Strobe.
X07-DS-001-21