VG3617161ET-6 Powerchip, VG3617161ET-6 Datasheet - Page 13

• Manufacturer Part Number: VG3617161ET-6
• Description: 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
• Manufacturer: Powerchip

VIS
3.Initiallization
4.Programming the Mode Register
Document:1G5-0189
Wrap Type (Burst Sequence)
is completed, the output bus will become high impedance.
as either “Sequential” or “Interleave”. The method chosen will depend on the type of CPU in the system.
leaved addressing. Both sequences support bursts of 1,2,4 and 8. Only the sequential burst. supports the
full-page length.
Burst Length
200us minimum delay is needed in which stable power and input signals are maintained. During this delay,
CKE and DQM recommend to be held high.
is completed and the minimum t
A0 as data inputs. The register retains data until it is reprogrammed or until the device loses power.
The mode register has four fields;
have elapsed.
CAS Latency
before the data will be available. The SDRAM is capable of reconfiguring its internal architecture based on
the value of CAS latency.
can be programmed as 2 or 3.
The mode register is programmed by the mode register set command using address bits A11 through
Burst Length is the number of words that will be output or input in read or write cycle. After a read burst
The burst length is programmable as 1,2,4,8 or full page.
The synchronous DRAM is initialized in the power on sequence. Once power has been applied, a
After the 200us delay, both banks must be precharged using the precharge command. Once precharge
Minimum 8 CBR refresh cycles must be performed before or after the mode register set command.
The wrap type specifies the order in which the burst data will be addressed. The order is programmable
Some microprocessor cache systems are optimized for sequential addressing and others for inter-
Following mode register programming, no command can be asserted befor at least two clock cycles
CAS latency is the most critical parameter to be set. It tells the device how many clocks must elapse
The value is determined by the frequency of the clock and the speed grade of the device. The value
Options
CAS latency
Wrap type
Burst length
: A2 through A0
: A11 through A7
: A6 through A4
: A3
RP
is satisfied, the mode register can be programmed.
Rev.2
CMOS Synchronous Dynamic RAM
1,048,576 x 16 - Bit
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VG3617161ET