VG3617161ET-6 Powerchip, VG3617161ET-6 Datasheet - Page 6

• Manufacturer Part Number: VG3617161ET-6
• Description: 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
• Manufacturer: Powerchip

8. Transition times are measured between V
9. t
10. Power up sequence
VIS
6. Power-up sequence is described in Note 10.
7. A.C. Test Conditions
Document:1G5-0189
Output
HZ
Transition Time (Rise and Fall) of Input Signals
Power up must be performed in the following sequence.
1) Power must be applied to V
2) After power-up, a pause of 200u secouds minimum is required. Then, it is recommended that DQM is held
3) Both banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode Register.
5) A minimum of 8 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the device. Sequence of
defines the time at which the outputs achieve the open circuit condition and are not reference levels.
4 and 5 may be changed.
CKE = ”H”, DQM = ”H”. The CLK signals must be started at the same time.
“high” (V
LVTTL D.C. Test Load (A)
Reference Level of Output Signals
Reference Level of Input Signals
DD
Input Signal Levels
30pF
levels) to ensure DQ output to be in the high impedance.
Output Load
DD
1.2K
870
3.3V
and V


DDQ
IH
and V
(simultaneously) when all input signals are held “NOP” state and
IL
Output
. Transition (rise and fall) of input signals are fixed slope (1 ns).
Rev.2
Reference to the Under Output Load (B)
LVTTL A.C. Test Load (B)
ZO=50

2.4V / 0.4V
1.4V
1.4V
CMOS Synchronous Dynamic RAM
1ns
30pF
1.4V
50

1,048,576 x 16 - Bit
Page 6
VG3617161ET