LM3S1165 Luminary Micro, Inc, LM3S1165 Datasheet - Page 156
![no-image](/images/no-image-200.jpg)
LM3S1165
Manufacturer Part Number
LM3S1165
Description
Lm3s1165 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S1165.pdf
(530 pages)
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Reset
Reset
Type
Type
Internal Memory
Flash Memory Protection Read Enable 0 (FMPRE0)
Base 0x400F.E000
Offset 0x130 and 0x200
Type R/W, reset 0xFFFF.FFFF
156
Bit/Field
31:0
R/W
R/W
31
15
1
1
R/W
R/W
Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130
and 0x200
Note:
Note:
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). This register is loaded during the power-on reset sequence. The factory settings
for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves
a policy of open access and programmability. The register bits may be changed by writing the
specific register bit. However, this register is R/W0; the user can only change the protection bit from
a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence. For additional
information, see the "Flash Memory Protection" section.
30
14
1
1
READ_ENABLE
R/W
R/W
29
13
1
1
Name
This register is aliased for backwards compatability.
Offset is relative to System Control base address of 0x400FE000.
R/W
R/W
28
12
1
1
R/W
R/W
27
11
1
1
Type
R/W
R/W
R/W
26
10
1
1
0xFFFFFFFF
Reset
R/W
R/W
25
1
9
1
Preliminary
READ_ENABLE
READ_ENABLE
R/W
R/W
24
1
8
1
Description
Flash Read Enable
Enables 2-KB flash blocks to be executed or read. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value
0xFFFFFFFF
R/W
R/W
23
1
7
1
R/W
R/W
Description
Enables 64 KB of flash.
22
1
6
1
R/W
R/W
21
1
5
1
R/W
R/W
20
1
4
1
R/W
R/W
19
1
3
1
R/W
R/W
18
1
2
1
July 26, 2008
R/W
R/W
17
1
1
1
R/W
R/W
16
1
0
1
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