LM3S1165 Luminary Micro, Inc, LM3S1165 Datasheet - Page 444

• Manufacturer Part Number: LM3S1165
• Description: Lm3s1165 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
Pulse Width Modulator (PWM)
PWM0 Interrupt and Trigger Enable (PWM0INTEN)
Base 0x4002.8000
Offset 0x044
Type R/W, reset 0x0000.0000
444
Bit/Field
31:14
13
12
11
RO
RO
31
15
0
0
reserved
Register 13: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044
Register 14: PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084
Register 15: PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4
These registers control the interrupt and ADC trigger generation capabilities of the PWM generators
(PWM0INTEN controls the PWM generator 0 block, and so on). The events that can cause an
interrupt or an ADC trigger are:
■
■
■
■
■
■
Any combination of these events can generate either an interrupt, or an ADC trigger; though no
determination can be made as to the actual event that caused an ADC trigger if more than one is
specified.
RO
RO
30
14
0
0
The counter being equal to the load register
The counter being equal to zero
The counter being equal to the comparator A register while counting up
The counter being equal to the comparator A register while counting down
The counter being equal to the comparator B register while counting up
The counter being equal to the comparator B register while counting down
TrCmpBD
TrCmpBD
TrCmpBU
TrCmpAD
R/W
reserved
RO
29
13
0
0
Name
TrCmpBU
R/W
RO
28
12
0
0
TrCmpAD
R/W
RO
27
11
0
0
Type
R/W
R/W
R/W
RO
TrCmpAU
R/W
RO
26
10
0
0
TrCntLoad
Reset
0x00
R/W
RO
25
0
9
0
0
0
0
Preliminary
TrCntZero
R/W
RO
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Trigger for Counter=Comparator B Down
When 1, a trigger pulse is output when the counter matches the
comparator B value and the counter is counting down.
Trigger for Counter=Comparator B Up
When 1, a trigger pulse is output when the counter matches the
comparator B value and the counter is counting up.
Trigger for Counter=Comparator A Down
When 1, a trigger pulse is output when the counter matches the
comparator A value and the counter is counting down.
reserved
RO
RO
23
0
7
0
reserved
RO
RO
22
0
6
0
IntCmpBD
R/W
RO
21
0
5
0
IntCmpBU
R/W
RO
20
0
4
0
IntCmpAD
R/W
RO
19
0
3
0
IntCmpAU
R/W
RO
18
0
2
0
IntCntLoad
July 26, 2008
R/W
RO
17
0
1
0
IntCntZero
R/W
RO
16
0
0
0