LM3S818 Luminary Micro, Inc, LM3S818 Datasheet - Page 88

• Manufacturer Part Number: LM3S818
• Description: Lm3s818 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

System Control
a.
88
Reset
Reset
Type
Type
Bit/Field
If the unit is unclocked, reads or writes to the unit will generate a bus fault.
31:5
Run-Mode, Sleep-Mode, and Deep-Sleep-Mode Clock Gating Control 2 (RCGC2, SCGC2, and DCGC2)
Offset 0x108, 0x118, and 0x128
4
3
2
1
0
RO
RO
31
15
0
0
Register 25: Run-Mode Clock Gating Control 2 (RCGC2), offset 0x108
Register 26: Sleep-Mode Clock Gating Control 2 (SCGC2), offset 0x118
Register 27: Deep-Sleep-Mode Clock Gating Control 2 (DCGC2), offset 0x128
These registers control the clock gating logic. Each bit controls a clock enable for a given
interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will
generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that
all functional units are disabled. It is the responsibility of software to enable the ports necessary for
the application. Note that these registers may contain more bits than there are interfaces,
functions, or units to control. This is to assure reasonable code compatibility with other family and
future parts.
RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and
DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration
(RCC) register (see page 78) specifies that the system uses sleep modes.
RO
RO
30
14
0
0
reserved
PORTE
PORTD
PORTC
PORTB
PORTA
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
Type
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
27
11
0
0
reserved
RO
RO
26
10
0
0
Reset
RO
RO
25
0
9
0
0
0
0
0
0
0
Preliminary
RO
RO
24
0
8
0
Description
Reserved bits return an indeterminate value, and should
never be changed.
This bit controls the clock gating for the GPIO Port E
module. If set, the unit receives a clock and functions.
Otherwise, the unit is unclocked and disabled.
This bit controls the clock gating for the GPIO Port D
module. If set, the unit receives a clock and functions.
Otherwise, the unit is unclocked and disabled.
This bit controls the clock gating for the GPIO Port C
module. If set, the unit receives a clock and functions.
Otherwise, the unit is unclocked and disabled.
This bit controls the clock gating for the GPIO Port B
module. If set, the unit receives a clock and functions.
Otherwise, the unit is unclocked and disabled.
This bit controls the clock gating for the GPIO Port A
module. If set, the unit receives a clock and functions.
Otherwise, the unit is unclocked and disabled.
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
PORTE PORTD PORTC PORTB PORTA
R/W
RO
20
0
4
0
R/W
RO
19
0
3
0
R/W
RO
18
0
2
0
February 6, 2007
a
a
a
a
a
R/W
RO
17
0
1
0
R/W
RO
16
0
0
0