LM3S818 Luminary Micro, Inc, LM3S818 Datasheet - Page 97

• Manufacturer Part Number: LM3S818
• Description: Lm3s818 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

February 6, 2007
Reset
Reset
Reset
Reset
Type
Type
Type
Type
Bit/Field
31:0
Flash Memory Protection Read Enable and Program Enable (FMPRE and FMPPE)
Flash Memory Protection Read Enable and Program Enable (FMPRE and FMPPE)
Offset 0x130 and 0x134
Offset 0x130 and 0x134
Block31
Block15
R/W0
R/W0
RO
RO
31
31
15
15
0
0
1
1
Block30
Block14
Register 1: Flash Memory Protection Read Enable (FMPRE), offset 0x130
Register 2: Flash Memory Protection Program Enable (FMPPE), offset 0x134
Note:
These registers store the read-only (FMPRE) and execute-only (FMPPE) protection bits for each
2-KB flash block. This register is loaded during the power-on reset sequence.
The factory settings for the FMPRE and FMPPE registers are a value of 1 for all implemented
banks. This implements a policy of open access and programmability. The register bits may be
changed by writing the specific register bit. However, this register is R/W0; the user can only
change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1).
The changes are not permanent until the register is committed (saved), at which point the bit
change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by
executing a power-on reset sequence.
For additional information, see “Flash Memory Protection” on page 93.
R/W0
R/W0
RO
RO
30
30
14
14
0
0
1
1
Block31-
Block0
Name
Block29
Block13
R/W0
R/W0
RO
RO
Offset is relative to System Control base address of 0x400FE000
29
29
13
13
0
1
0
1
Block28
Block12
R/W0
R/W0
RO
RO
28
28
12
12
0
1
0
1
reserved
Block27
Block11
R/W0
R/W0
R/W0
RO
RO
27
27
11
11
Type
0
0
1
1
Block26
Block10
R/W0
R/W0
RO
RO
26
26
10
10
0
1
0
1
Block25
Block9
R/W0
R/W0
RO
RO
25
25
0
1
9
9
0
1
Preliminary
Reset
1
Block24
Block8
R/W0
R/W0
RO
RO
24
24
0
1
8
8
0
1
reserved
Block23
Block7
Block7
R/W0
R/W0
R/W0
RO
23
23
0
1
7
7
1
1
Description
Enable 2-KB flash blocks to be written or erased
(FMPPE register), or executed or read (FMPRE
register). The policies may be combined as shown
in Table 7-1 on page 94.
Block22
Block6
Block6
R/W0
R/W0
R/W0
RO
22
22
0
1
6
6
1
1
Block21
Block5
Block5
R/W0
R/W0
R/W0
RO
21
21
0
1
5
5
1
1
Block20
Block4
Block4
R/W0
R/W0
R/W0
RO
20
20
0
1
4
4
1
1
Block19
Block3
Block3
R/W0
R/W0
R/W0
RO
0
19
19
1
3
3
1
1
LM3S818 Data Sheet
Block18
Block2
Block2
R/W0
R/W0
R/W0
RO
0
18
18
1
2
2
1
1
Block17
Block1
Block1
R/W0
R/W0
R/W0
RO
0
17
17
1
1
1
1
1
Block15
Block0
Block0
R/W0
R/W0
R/W0
RO
0
16
16
1
0
0
1
1
97