IDT72V291L20PF IDT, Integrated Device Technology Inc, IDT72V291L20PF Datasheet - Page 23

• Manufacturer Part Number: IDT72V291L20PF
• Description: IC FIFO SS 32768X36 20NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V291L20PF

• Function: Synchronous
• Memory Size: 1.1M (32K x 36)
• Data Rate: 50MHz
• Access Time: 20ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Configuration: Dual
• Density: 1.125Mb
• Access Time (max): 12ns
• Word Size: 9b
• Organization: 128Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 50MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 55mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V291L20PF

NOTES:
1. m = PAF offset .
2. D = maximum FIFO depth.
3. t
4. PAF is asserted and updated on the rising edge of WCLK only.
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. t
5. PAE is asserted and updated on the rising edge of WCLK only.
NOTES:
1. For IDT Standard mode: D = maximum FIFO depth. D = 65,536 for the IDT72V281 and 131,072 for the IDT72V291.
2. For FWFT mode: D = maximum FIFO depth. D = 65,537 for the IDT72V281 and 131,073 for the IDT72V291.
IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO
65,536 x 9 and 131,072 x 9
WCLK
WCLK
WCLK
RCLK
RCLK
RCLK
In IDT Standard mode: D = 65,536 for the IDT72V281 and 131,072 for the IDT72V291.
In FWFT mode: D = 65,537 for the IDT72V281 and 131,073 for the IDT72V291.
RCLK and the rising edge of WCLK is less than t
WCLK and the rising edge of RCLK is less than t
WEN
SKEW2
WEN
SKEW2
WEN
REN
REN
PAF
REN
PAE
HF
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus t
t
CLKH
t
CLKH
t
ENS
n words in FIFO
n+1 words in FIFO
t
ENS
Figure 19. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
Figure 18. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
t
CLKL
D - (m+1) words in FIFO
t
t
CLKL
ENH
[
t
(2)
SKEW2
D-1
1
,
Figure 20. Half-Full Flag Timing (IDT Standard and FWFT Modes)
2
(3)
D/2 words in FIFO
t
SKEW2
SKEW2
ENH
+ 1
(4)
]
, then the PAF deassertion time may be delayed one extra WCLK cycle.
, then the PAE deassertion may be delayed one extra RCLK cycle.
words in FIFO
t
t
PAE
CLKH
1
TM
(2)
(1)
2
,
(2)
t
ENS
t
CLKL
2
23
t
PAF
t
t
ENH
ENS
t
HF
t
ENS
t
SKEW2
n+1 words in FIFO
n+2 words in FIFO
t
ENS
(3)
[
D/2 + 1 words in FIFO
D-1
t
ENH
2
+ 2
t
ENH
]
D - m words in FIFO
(2)
(3)
words in FIFO
,
1
t
HF
1
(1)
,
(2)
COMMERCIAL AND INDUSTRIAL
(2)
PAE
PAF
). If the time between the rising edge of
). If the time between the rising edge of
t
PAE
[
D-1
2
2
D/2 words in FIFO
TEMPERATURE RANGES
+ 1
2
t
PAF
]
words in FIFO
n words in FIFO
n+1 words in FIFO
D-(m+1) words
in FIFO
4513 drw 23
4513 drw 21
4513 drw 22
(1)
,
(2)
(2)
(2)
,
(3)