IDT72291L20TFI IDT, Integrated Device Technology Inc, IDT72291L20TFI Datasheet - Page 14

• Manufacturer Part Number: IDT72291L20TFI
• Description: IC FIFO 65536X18 LP 20NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72291L20TFI

• Function: Synchronous
• Memory Size: 1.1M (65K x 18)
• Data Rate: 50MHz
• Access Time: 20ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-STQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72291L20TFI

valid on the outputs. OR stays LOW after the RCLK LOW to HIGH transition
that shifts the last word from the FIFO memory to the outputs. OR goes
HIGH only with a true read (RCLK with REN = LOW). The previous data
stays at the outputs, indicating the last word was read. Further data reads
are inhibited until OR goes LOW again. See Figure 10, Read Timing
(FWFT Mode), for the relevant timing information.
mode, OR is a triple register-buffered output.
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (MRS), PAF will go LOW after (D – m) words are
written to the FIFO. The PAF will go LOW after (65,536–m) writes for the
IDT72281 and (131,072–m) writes for the IDT72291. The offset “m” is the
full offset value. The default setting for this value is stated in the footnote of
Table 1.
IDT72281 and (131,073–m) writes for the IDT72291, where m is the full
offset value. The default setting for this value is stated in the footnote of
Table 2.
and FWFT Mode), for the relevant timing information.
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
reaches the almost-empty condition. In IDT Standard mode, PAE will go
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
In IDT Standard mode, EF is a double register-buffered output. In FWFT
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
In FWFT mode, the PAF will go LOW after (65,53–m) writes for the
See Figure 18, Programmable Almost-Full Flag Timing (IDT Standard
PAF is synchronous and updated on the rising edge of WCLK.
The Programmable Almost-Empty flag (PAE) will go LOW when the FIFO
EF/OR is synchronous and updated on the rising edge of RCLK.
14
LOW when there are n words or less in the FIFO. The offset “n” is the
empty offset value. The default setting for this value is stated in the footnote
of Table 1.
in the FIFO. The default setting for this value is stated in the footnote of
Table 2.
dard and FWFT Mode), for the relevant timing information.
HALF-FULL FLAG (HF)
FIFO beyond half-full sets HF LOW. The flag remains LOW until the differ-
ence between the write and read pointers becomes less than or equal to
half of the total depth of the device; the rising RCLK edge that accomplishes
this condition sets HF HIGH.
PRS), HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 65,536
for the IDT72281 and 131,072 for the IDT72291.
will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 65,537 for the
IDT72281 and 131,073 for the IDT72291.
for the relevant timing information. Because HF is updated by both RCLK
and WCLK, it is considered asynchronous.
DATA OUTPUTS (Q
In FWFT mode, the PAE will go LOW when there are n+1 words or less
See Figure 19, Programmable Almost-Empty Flag Timing (IDT Stan-
PAE is synchronous and updated on the rising edge of RCLK.
This output indicates a half-full FIFO. The rising WCLK edge that fills the
In IDT Standard mode, if no reads are performed after reset (MRS or
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF
See Figure 20, Half-Full Flag Timing (IDT Standard and FWFT Modes),
(Q
0
- Q
8
) are data outputs for 9-bit wide data.
0
-Q
8
)
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TEMPERATURE RANGES