MT18VDDT6472 Micron, MT18VDDT6472 Datasheet - Page 20

• Manufacturer Part Number: MT18VDDT6472
• Description: 200-Pin DDR SDRAM SODIMMs (x72)
• Manufacturer: Micron

SPD CLOCK AND DATA CONVENTIONS
SCL LOW. SDA state changes during SCL HIGH are re-
served for indicating start and stop conditions
(Figures 1 and 2).
SPD START CONDITION
which is a HIGH-to-LOW transition of SDA when SCL is
HIGH. The SPD device continuously monitors the SDA
and SCL lines for the start condition and will not respond
to any command until this condition has been met.
SPD STOP CONDITION
tion, which is a LOW-to-HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place the
SPD device into standby power mode.
32, 64 Meg x 72 DDR SDRAM DIMMs
DD18C32_64X72AG_B.p65–Rev. B, Pub. 1/02
SDA
SCL
Data states on the SDA line can change only during
All commands are preceded by the start condition,
All communications are terminated by a stop condi-
SCL from Master
Data Output
from Transmitter
Data Output
from Receiver
DATA STABLE
Data Validity
Figure 1
DATA
CHANGE
Acknowledge Response From Receiver
DATA STABLE
Figure 3
20
SPD ACKNOWLEDGE
cate successful data transfers. The transmitting device,
either master or slave, will release the bus after transmit-
ting eight bits. During the ninth clock cycle, the receiver
will pull the SDA line LOW to acknowledge that it re-
ceived the eight bits of data (Figure 3).
edge after recognition of a start condition and its slave
address. If both the device and a WRITE operation have
been selected, the SPD device will respond with an ac-
knowledge after the receipt of each subsequent eight-bit
word. In the read mode the SPD device will transmit eight
bits of data, release the SDA line and monitor the line for
an acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the slave will
continue to transmit data. If an acknowledge is not de-
tected, the slave will terminate further data transmis-
sions and await the stop condition to return to standby
power mode.
SDA
SCL
Acknowledge is a software convention used to indi-
The SPD device will always respond with an acknowl-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-pin DDR SDRAM DIMMs
Definition of Start and Stop
START
BIT
256MB, 512MB (ECC x72)
8
Figure 2
Acknowledge
9
©2002, Micron Technology, Inc.
STOP
BIT