IDT72V293L10PFI IDT, Integrated Device Technology Inc, IDT72V293L10PFI Datasheet - Page 26
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IDT72V293L10PFI
Manufacturer Part Number
IDT72V293L10PFI
Description
IC FIFO 65536X18 10NS 80QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V293L7-5PF.pdf
(45 pages)
Specifications of IDT72V293L10PFI
Function
Synchronous
Memory Size
1.1M (65K x 18)
Data Rate
166MHz
Access Time
10ns
Voltage - Supply
3.15 V ~ 3.45 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
80-TQFP, 80-VQFP
Configuration
Dual
Density
1.125Mb
Access Time (max)
6.5ns
Word Size
18/9Bit
Organization
64Kx18/128Kx9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
100MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.15V
Operating Supply Voltage (max)
3.45V
Supply Current
30@9BIT/35@18BITmA
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
80
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V293L10PFI
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72V293L10PFI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V293L10PFI8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTES:
1. t
2. LD = HIGH.
3. First data word latency: t
NOTES:
1. t
2. LD = HIGH, EF = HIGH
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
D
Q
Q
D
WCLK
WCLK
0
0
RCLK
RCLK
0
of WCLK and the rising edge of RCLK is less than t
of the RCLK and the rising edge of the WCLK is less than t
0
WEN
SKEW1
WEN
SKEW1
REN
REN
- Q
- D
- Q
- D
OE
FF
EF
n
n
n
n
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus t
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus t
t
ENS
DATA IN OUTPUT REGISTER
t
ENS
t
SKEW1
t
SKEW1
t
OLZ
ENH
t
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
REF
t
A
(1)
t
OE
+ 1*T
RCLK
t
t
SKEW1
ENH
t
ENS
t
t
DS
A
+ t
D
1
(1)
REF
0
NO WRITE
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
NO OPERATION
.
t
t
DHS
ENH
SKEW1
LAST WORD
1
, then EF deassertion may be delayed one extra RCLK cycle.
SKEW1
2
t
, then the FF deassertion may be delayed one extra WCLK cycle.
WFF
t
t
DS
OHZ
t
t
DS
ENS
D
DX
1
NO OPERATION
t
CLKH
t
WFF
t
t
ENH
DH
DATA READ
26
t
t
DH
CLK
2
TM
t
CLKL
t
CLKH
t
t
NARROW BUS FIFO
REF
ENS
t
OLZ
t
SKEW1
t
CLK
(1)
t
CLKL
t
ENS
t
ENH
LAST WORD
t
A
1
NO WRITE
t
ENH
t
A
COMMERCIAL AND INDUSTRIAL
WFF
REF
2
t
WFF
). If the time between the rising edge
). If the time between the rising edge
TEMPERATURE RANGES
t
FEBRUARY 11, 2009
ENS
t
DS
NEXT DATA READ
D
0
DX+1
t
WFF
t
REF
t
t
ENH
A
4666 drw10
t
DH
4666 drw11
D
1