MT28F128J3FS-12 ET Micron, MT28F128J3FS-12 ET Datasheet - Page 40
![no-image](/images/no-image-200.jpg)
MT28F128J3FS-12 ET
Manufacturer Part Number
MT28F128J3FS-12 ET
Description
128Mb Q-Flash - OBSOLETE
Manufacturer
Micron
Datasheet
1.MT28F128J3FS-12_ET.pdf
(55 pages)
- Current page: 40 of 55
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tion, and after V
must be placed in read array mode via the READ
ARRAY command if subsequent access to the memory
array is desired. During V
kept at or below V
Power-Up/Down Protection
protection against accidental block erasure, program-
ming, or lock bit configuration. Internal circuitry
resets the CEL to read array mode at power-up. A sys-
tem designer must watch out for spurious writes for
V
WE# must be low and the device enabled (see Table 2
on page 11) for a command write, driving WE# to V
09005aef80b5a323
MT28F640J3.fm – Rev. N 3/05 EN
CC
After block erase, program, or lock bit configura-
During power transition, the device itself provides
voltages above V
PEN
CC
.
LKO
transitions to V
PEN
when V
transitions, V
PEN
is active. Because
PENLK
PEN
, the CEL
must be
IH
40
or disabling the device inhibits WRITEs. The CEL’s
two-step command sequence architecture provides
added protection against data alteration. In-system
block lock and unlock capability protects the device
against inadvertent programming. The device is dis-
abled when RP# = V
Keeping V
change.
Power Dissipation
tion not only during device operation, but also for data
retention during system idle time. Flash memory’s
non-volatility increases usable battery life because
data is retained when system power is removed.
Designers must consider battery power consump-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
PEN
below V
128Mb, 64Mb, 32Mb
IL
PENLK
Q-FLASH MEMORY
regardless of its control inputs.
prevents inadvertent data
©2000 Micron Technology. Inc.
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