MT9042CPR Zarlink Semiconductor, Inc., MT9042CPR Datasheet
MT9042CPR
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MT9042CPR Summary of contents
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Features • Meets jitter requirements for: AT&T TR62411 Stratum 3, 4 and Stratum 4 Enhanced for DS1 interfaces; and for ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 for E1 interfaces • Provides C1.5, C3, C2, C4, ...
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MT9042C Pin Description Pin # Name 1,15 V Ground. 0 Volts TRST TIE Circuit Reset (TTL Input). A logic low at this input resets the Time Interval Error (TIE) correction circuit resulting in a re-alignment of input phase ...
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Pin Description Pin # Name 16 C8o Clock 8.192MHz (CMOS Output). This output is used for ST-BUS operation at 8.192Mb/s. 17 C16o Clock 16.384MHz (CMOS Output). This output is used for ST-BUS operation at 16.384Mb/s. 19 GTi Guard Time (Schmitt ...
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MT9042C Functional Description The MT9042C is a Multitrunk System Synchronizer, providing timing (clock) and synchronization (frame) signals to interface circuits for T1 and E1 Primary Rate Digital Transmission links. Figure functional block diagram which is described in ...
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Virtual Reference Phase from Detector TIE Corrector Feedback Signal from Frequency Select MUX from Normal to Holdover. In Holdover Mode, the DPLL no longer uses the virtual reference signal, but generates an accurate clock signal using storage techniques. The Compare ...
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MT9042C Digitally Controlled Oscillator (DCO) - the DCO receives the limited and filtered signal from the Loop FIlter, and based on its value, generates a corresponding digital output synchronization method of the DCO is dependent on the state of the ...
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DPLL and the Guard Time Circuit. Control is based on the logic levels at the control inputs LOS1, LOS2, RSEL, MS1, MS2 and GTi of the Guard Time Circuit (See Figure 6 TIE To DPLL Reference Corrector State ...
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MT9042C Automatic Control Automatic Control should be used when simple MT9042C control is required, which is more complex than the very simple control provide by Manual Control with no external circuitry, but not as complex as Manual Control with a ...
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Description Input Controls MS2 MS1 RSEL GTi Legend Change / Not Valid MTIE State ...
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MT9042C Description Input Controls LOS2 LOS1 GTi RST Legend Change MTIE State ...
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MT9042C Measures of Performance The following are some synchronizer performance indicators and their corresponding definitions. Intrinsic Jitter Intrinsic jitter is the jitter produced synchronizing circuit and is measured at its output measured by applying a reference signal with ...
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MT9042C Holdover Accuracy Holdover accuracy is defined as the absolute tolerance of an output clock signal, when it is not locked to an external reference signal, but is operating using storage techniques. MT9042C, the storage value is determined while the ...
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MT9042C and Network Specifications The MT9042C fully meets all applicable PLL requirements (intrinsic jitter, jitter tolerance, jitter transfer, frequency accuracy, holdover accuracy, capture range, phase change slope and MTIE during reference rearrangement) for specifications. 1. AT&T TR62411 (DS1) December 1990 ...
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MT9042C CTS CXO-65-HG-5-C-20.0MHz Frequency: 20MHz Tolerance: 25ppm 0C to 70C Rise & Fall Time: 8ns (0.5V 4.5V 50pF) Duty Cycle: 45% to 55% The output clock should be connected directly (not AC coupled) to the OSCi input of the MT9042C, ...
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SEC SIGNAL STATUS LOS2 PRI SIGNAL GOOD STATUS LOS1 GTo V SIH GTi MT9042C PRI STATE NORMAL HOLDOVER NOTES represents the time delay from when the reference goes D bad to when the MT9042C is provided with a ...
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MT9042C MT9074 To Line 1 DSTo TTIP DSTi To TRING TX Line XFMR F0i RTIP C4i To RRING RX Line XFMR E1.5o LOS MT9074 To Line 2 DSTo TTIP DSTi TRING To TX Line XFMR F0i RTIP C4i RRING To ...
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To Line 1 MT9075 DSTo TTIP To DSTi TX Line TRING XFMR F0i RTIP C4i To RRING RX Line RxFP XFMR LOS MT9075 To Line 2 DSTo TTIP DSTi To TRING TX Line XFMR F0i RTIP C4i RRING To RX ...
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MT9042C Dual T1 Reference Sources with MT9042C in Automatic Control For systems requiring simple state machine control, the application circuit shown in Figure 14 using Automatic Control may be used. In this circuit, the MT9042C Automatically, is using a Guard ...
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MT9042C Absolute Maximum Ratings* - Parameter 1 Supply voltage 2 Voltage on any pin 3 Current on any pin 4 Storage temperature 5 PLCC package power dissipation * Exceeding these values may cause permanent damage. Functional operation under these conditions ...
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AC Electrical Characteristics - Performance Characteristics 1 Freerun Mode accuracy with OSCi at Holdover Mode accuracy with OSCi at Capture range with OSCi at Phase lock time 11 Output phase continuity ...
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MT9042C AC Electrical Characteristics - Input/Output Timing Characteristics 1 Reference input pulse width high or low 2 Reference input rise or fall time 3 8kHz reference input to F8o delay 4 1.544MHz reference input to F8o delay 5 2.048MHz reference ...
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PRI/SEC 8kHz PRI/SEC 1.544MHz PRI/SEC 2.048MHz F8o NOTES: 1. Input to output delay values are valid after a TRST or RST with no further state changes Figure 19 - Input to Output Timing (Normal Mode) F8o F0o F16o t C16WL ...
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MT9042C F8o MS1,2 LOS1,2 RSEL, GTi Figure 21 - Input Controls Setup and Hold Timing AC Electrical Characteristics - Intrinsic Jitter Unfiltered Characteristics 1 Intrinsic jitter at F8o (8kHz) 2 Intrinsic jitter at F0o (8kHz) 3 Intrinsic jitter at F16o ...
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AC Electrical Characteristics - 8kHz Input to 8kHz Output Jitter Transfer Characteristics 1 Jitter attenuation for 1Hz@0.01UIpp input 2 Jitter attenuation for 1Hz@0.54UIpp input 3 Jitter attenuation for 10Hz@0.10UIpp input 4 Jitter attenuation for 60Hz@0.10UIpp input 5 Jitter attenuation for ...
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MT9042C AC Electrical Characteristics - 8kHz Input Jitter Tolerance Characteristics 1 Jitter tolerance for 1Hz input 2 Jitter tolerance for 5Hz input 3 Jitter tolerance for 20Hz input 4 Jitter tolerance for 300Hz input 5 Jitter tolerance for 400Hz input ...
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AC Electrical Characteristics - OSCi 20MHz Master Clock Input Characteristics 1 Frequency accuracy (20 MHz nominal Duty cycle 5 Rise time 6 Fall time † See "Notes" following AC Electrical Characteristics tables. † Notes: Voltages are with ...
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