MT9042CPR Zarlink Semiconductor, Inc., MT9042CPR Datasheet - Page 4

• Manufacturer Part Number: MT9042CPR
• Description: Dual Reference Frequency Selectable Digital PLL with Multiple Clock Outputs for T1/E1 (ITU-T G.812 type IV) and Stratum (3, 4, 4E) Applications
• Manufacturer: Zarlink Semiconductor, Inc.

MT9042C
Functional Description
The MT9042C is a Multitrunk System Synchronizer,
providing timing (clock) and synchronization (frame)
signals to interface circuits for T1 and E1 Primary
Rate Digital Transmission links.
Figure 1 is a functional block diagram which is
described in the following sections.
Reference Select MUX Circuit
The MT9042C accepts two simultaneous reference
input signals and operates on their falling edges.
Either the primary reference (PRI) signal or the
secondary reference (SEC) signal can be selected
as input to the TIE Corrector Circuit. The selection is
based on the Control, Mode and Reference
Selection of the device. See Tables 1, 4 and 5.
Frequency Select MUX Circuit
The MT9042C operates with one of three possible
input reference frequencies (8kHz, 1.544MHz or
2.048MHz). The frequency select inputs (FS1 and
FS2) determine which of the three frequencies may
be used at the reference inputs (PRI and SEC). Both
inputs must have the same frequency applied to
them. A reset (RST) must be performed after every
frequency select input change. Operation with FS1
and FS2 both at logic low is reserved and must not
be used. See Table 1.
4
PRI or SEC
Select Mux
Reference
from
Programmable
Delay Circuit
Figure 3 - TIE Corrector Circuit
State Machine
TIE Corrector
Enable
Control
TRST
from
Circuit
Resets Delay
Time Interval Error (TIE) Corrector Circuit
The TIE corrector circuit, when enabled, prevents a
step change in phase on the input reference signals
(PRI or SEC) from causing a step change in phase at
the input of the DPLL block of Figure 1.
During reference input rearrangement, such as
during a switch from the primary reference (PRI) to
the secondary reference (SEC), a step change in
phase on the input signals will occur. A phase step
at the input of the DPLL will lead to unacceptable
phase changes in the output signal.
As shown in Figure 3, the TIE Corrector Circuit
receives one of the two reference (PRI or SEC)
signals, passes the signal through a programmable
delay line, and uses this delayed signal as an
internal virtual reference, which is input to the DPLL.
Therefore, the virtual reference is a delayed version
of the selected reference.
During a switch, from one reference to the other, the
State Machine first changes the mode of the device
Delay Value
FS2
0
1
0
1
Control Signal
Table 1 - Input Frequency Selection
Select MUX
Signal from
FS1
Compare
Frequency
Feedback
Circuit
0
1
0
1
Input Frequency
1.544MHz
2.048MHz
Reserved
8kHz
Reference
to DPLL
Virtual