MT9080BPR Zarlink Semiconductor, Inc., MT9080BPR Datasheet - Page 15

• Manufacturer Part Number: MT9080BPR
• Description: SMX-Switch, SMX-Switch Matrix Module
• Manufacturer: Zarlink Semiconductor, Inc.

into its memories addressed by the internal counter.
The SMX in the external mode reads data out from
memory locations addressed by the Connection
memory. In this manner, incoming data is continually
written into one memory block while it is being read
out of the other block. The device in counter mode
has its output drivers disabled.
This configuration results in a maximum throughput
delay of two frames. Data clocked into the device in
the current frame is clocked out in the next frame.
The appropriate timing parameters are illustrated in
Figure 19. The clock signal applied to all three SMXs
has the same frequency.
SMX#3 is operated in Connect Memory Mode-2. In
this mode, data is clocked out of the device at the
same rate as the clock, i.e., at 16.384 Mbps.
Extended Switching Matrix
Larger extended switch matrices can be created
using the 1024/2048 channel switch as a building
block. As shown in Figure 20, a 4096 channel matrix
would require four smaller 2048 channel building
blocks.
Construction of matrices larger than 4K may require
external
capacitive loading on the outputs.
Using the SMX for Messaging
In some system architectures the PCM voice signals
and system status information is transmitted and
received over a common backplane. To facilitate
microprocessor access to the backplane, the SMX
can be used to read incoming data or write to a
channel on the output data bus.
Data clocked into the SMX can be read from the
device by a microprocessor interfaced to the output
data bus and the address bus (see Figure 21). Data
can be written to a specific timeslot on the output
data bus directly by the microprocessor using the
messaging feature (enabled by tying the ME pin
high).
A 1024 Switch Matrix with messaging capability can
be constructed with three SMXs as shown in Figure
22. The first SMX is used for performing the actual
switching function. The second SMX is configured as
the connection memory. As discussed in the 1024
switch application, by enabling the messaging
feature, data clocked out of the connection memory
and latched into the data memory address bus will
be clocked out on to the data bus directly. Incoming
data is read by the microprocessor using the third
drivers
to
accommodate
the
greater
SMX. The data output bus of the third SMX is
connected to the data bus of the MPU.
Figure 22 - A 1024 Channel Switch Matrix with
Figure 21 - Reading the Data Memory with a
Data in
Address
Decode
16
16
D0
D15
MESSAGING
i
-
SMX #3
i
D0-D15i
Z
Y
X
CS
DM-1
ADDR
Message Capability
ADDRESS DS HALT IRQ
D0
D15
Microprocessor
A0-A11
CK
o
-
o
DM-1/DM-2
CMOS
DATA
16
16
M P U
DS
DATA MEMORY
MPU
ADDR
16
ADDR
ADDR
DTA CD R/W
FP
SMX #1
DM-1/2
SMX #2
CONNECTION
MEMORY
CM-1/2
MT9080B
D0-D15o
DATA
+5V
ME
D0-D15
ODE
+5V
Data out
16
16
+5V
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