IDT72T54252L6-7BB IDT, Integrated Device Technology Inc, IDT72T54252L6-7BB Datasheet - Page 31

• Manufacturer Part Number: IDT72T54252L6-7BB
• Description: IC FIFO DDR/SDR QUAD/DUAL 324BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T54252L6-7BB

• Function: Asynchronous
• Memory Size: 20K (1K x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72T54252L6-7BB

THE INSTRUCTION REGISTER
processor at the rising edge of TCLK.
register to be accessed, or both. The instruction shifted into the register is latched
at the completion of the shifting process when the TAP controller is at Update-
IR state.
which can hold instruction data. These mandatory cells are located nearest the
serial outputs they are the least significant bits.
TEST DATA REGISTER
register, the Boundary Scan register and Device ID register.
and a common serial data output.
complete description, refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
Test Bypass Register
to TDO. It contains a single stage shift register for a minimum length in serial path.
When the bypass register is selected by an instruction, the shift register stage
is set to a logic zero on the rising edge of TCLK when the TAP controller is in
the Capture-DR state.
operation of the device in response to the BYPASS instruction.
The Boundary-Scan Register
out of the processor input/output ports. The Boundary Scan Register is a part
of the IEEE 1149.1-1990 Standard JTAG Implementation.
The Device Identification Register
specify the manufacturer, part number and version of the processor to be
determined through the TAP in response to the IDCODE instruction.
dropped in the 11-bit Manufacturer ID field.
tains the following values:
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
31(MSB)
Version (4 bits)
0X0
The Instruction register allows an instruction to be shifted in serially into the
The Instruction is used to select the test to be performed, or the test data
The instruction register must contain 4 bit instruction register-based cells
The Test Data register contains three test data registers: the Test Bypass
These registers are connected in parallel between a common serial input
The following sections provide a brief description of each element. For a
The register is used to allow test data to flow through the device from TDI
The operation of the bypass register should not have any effect on the
The Boundary Scan Register allows serial data TDI be loaded in to or read
The Device Identification Register is a Read Only 32-bit register used to
IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity is
For the IDT72T54242/72T54252/72T54262, the Part Number field con-
IDT72T54242/252/262 JTAG Device Identification Register
28 27
Part Number (16-bit) Manufacturer ID (11-bit)
IDT72T54242
IDT72T54252
IDT72T54262
Device
12 11
Part# Field
4C5 (hex)
4C6 (hex)
4C7 (hex)
00B3 (hex)
1 0(LSB)
1
™
31
DDR/SDR FIFO
JTAG INSTRUCTION REGISTER
when the TAP controller is in the Shift-IR state. The instruction is decoded to
perform the following:
16 different possible instructions. Instructions are decoded as follows.
a complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
EXTEST
test mode and selects the boundary-scan register to be connected between TDI
and TDO. During this instruction, the boundary-scan register is accessed to
drive test data off-chip via the boundary outputs and receive test data off-chip
via the boundary inputs. As such, the EXTEST instruction is the workhorse of
IEEE. Std 1149.1, providing for probe-less testing of solder-joint opens/shorts
and of logic cluster function.
SAMPLE/PRELOAD
normal functional mode and selects the boundary-scan register to be connected
between TDI and TDO. During this instruction, the boundary-scan register can
be accessed via a date scan operation, to take a sample of the functional data
entering and leaving the IC. This instruction is also used to preload test data into
the boundary-scan register before loading an EXTEST instruction.
IDCODE
and selects the optional device identification register to be connected between
TDI and TDO. The device identification register is a 32-bit shift register containing
information regarding the IC manufacturer, device type, and version code.
Accessing the device identification register does not interfere with the operation
of the IC. Also, access to the device identification register should be immediately
available, via a TAP data-scan operation, after power-up of the IC or after the
TAP has been reset using the optional TRST pin or by otherwise moving to the
Test-Logic-Reset state.
Hex
Value
0000
0001
0002
0003
0004
0007
0008
000F
The required EXTEST instruction places the IC into an external boundary-
The required SAMPLE/PRELOAD instruction allows the IC to remain in a
The optional IDCODE instruction allows the IC to remain in its functional mode
The Instruction register allows instruction to be serially input into the device
•
•
The Instruction Register is a 4 bit field (i.e. IR3, IR2, IR1, IR0) to decode
The following sections provide a brief description of each instruction. For
Select test data registers that may operate while the instruction is
current. The other test data registers should not interfere with chip
operation and the selected data register.
Define the serial test data register path that is used to shift data between
TDI and TDO during data register scanning.
Instruction
EXTEST
SAMPLE/PRELOAD Select boundary scan register
IDCODE
CLAMP
HI-IMPEDANCE
OFFSET READ
OFFSET WRITE
BYPASS
Private
JTAG Instruction Register Decoding
Function
Test external pins
Selects chip identification register
Fix the output chains to scan chain values
Puts all outputs in high-impedance state
Read PAE/PAF offset register values
Write PAE/PAF offset register values
Select bypass register
Several combinations are private (for IDT
internal use). Do not use codes other than
those identified above.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 11, 2009