MT8960 Zarlink Semiconductor, Inc., MT8960 Datasheet
MT8960
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MT8960 Summary of contents
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... Features ST-BUS compatible • • Transmit/Receive filters & PCM Codec in one I.C • Meets AT&T D3/D4 and CCITT G711 and G712 µ -Law: MT8960/62/64/67 • • A-Law: MT8961/63/65/67 • Low power consumption: Op typ. Stby.: 2.5 mW typ. • Digital Coding Options: MT8964/65/66/67 CCITT Code MT8960/61/62/63 Alternative Code • ...
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... MT8960/61/62/63/64/65/66/67 MT8960/61/64/65 1 CSTi 2 DSTi C2i 3 DSTo 4 5 VDD F1i SD3 8 SD2 9 18 PIN CERDIP/PDIP Pin Description Pin Name CSTi Control ST-BUS TTL-compatible digital input used to control the function of the filter/codec. Three modes of operation may be effected by applying to this input a logic high (V (GNDD 8-bit serial word, depending on the logic states of CA and F1i. Functions controlled are: powerdown, fi ...
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... MT8960/61/62/63/64/65/66/67 ISO -CMOS MT8960/62 Digital Output 11111111 11110000 11100000 11010000 11000000 10110000 10100000 10010000 10000000 00000000 00010000 00100000 00110000 01000000 01010000 01100000 01110000 01111111 -2.415V -1.207V 0V +1.207V +2.415V Bit 7... 0 Analog Input Voltage (V MSB LSB Figure 3 - µ -Law Encoder Transfer Characteristic ...
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... Bits 0-3 represent the step value of the analog sample within the selected chord. The MT8960-63 provide a sign plus magnitude PCM output code format. The MT8964/66 PCM output code conforms to the AT &T D3 specification, i.e., true sign bit and inverted magnitude bits ...
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... high impedance input with a varying Ref capacitive load pF. The recommended reference voltage for the MT8960 series of codecs is 2.5V ±0.5%. The output voltage from the reference source should have a maximum temperature coefficient of 100 ppm/C°. This voltage should have a total regulation tolerance of ±0.5% both for changes in the input voltage and output loading of the voltage reference source ...
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... Register B. Register A is unaffected. The input and output of PCM data is inhibited. ) The contents of Register B controls the six uncommitted outputs SD0-SD5 (four outputs, SD0- is SD3, on MT8960/61/64/65 versions of chip) and also R provide entry into one of the three test modes of the chip. CSTi Normal chip operation. ...
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... The output of the PCM encoder is disabled and thus the encoded data is lost. The PCM output at DSTo is determined by the PCM input data. Analog loopback is defined as follows: • PCM input data is latched, decoded and filtered as normal but not output MT8960/61/62/63/64/65/66/67 ISO -CMOS BIT ...
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... SD3-5 are used primarily to drive external analog circuitry. Examples may include the switching in or out of gain sections or filter sections (eg., ring trip filter) (Figure 7). MT8962/63/66/67 provides all six SD outputs. MT8960/61/64/65 each packaged in an 18-pin DIP provide only four control outputs, SD0-3. BITS 0-2 0 Inactive state - logic low (GNDD). ...
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... Register Select EE SD3 SD0 SD2 SD1 Figure 7 - Typical Use of the Special Drive Outputs 2 MT8960/61/62/63/64/65/66/67 ISO -CMOS External Control: 1) Register A. Powerdown is controlled by bits 6 and 7 ( when both at logic high) of Register A which in turn receives its control word input via CSTi, when F1i is low and CA input is ...
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... MT8960/61/62/63/64/65/66/67 Speech Switch - 8980 Controlling Micro- Processor Control & Signalling - 8980 Figure 8 - Example Architecture of a Simple Digital Switching System Using the MT8960-67 6-28 2 ISO -CMOS DSTi V X DSTo V R CDTi SD0 . . • • . • SDn MT8960- • • • Repeated for Lines ...
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... I G Voltage Input High Voltage All Inputs T 4 Input Intermediate CA A Voltage L 5 Output Leakage DSTo Current (Tristate) SD 3-5 ° ± * Typical figures are with nominal 2 MT8960/61/62/63/64/65/66/67 ISO -CMOS Symbol V -GNDD DD V -GNDD EE V Ref V X Except 0 4 ...
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... MT8960/61/62/63/64/65/66/67 DC Electrical Characteristics (cont’d) Characteristics 6 Output Low DSTo D Voltage Output High DSTo I Voltage Output Resistance Output Capacitance DSTo 10 Input Current Input Resistance Input Capacitance Input Offset Voltage Output Resistance ...
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... CCITT G712 (Method 2) AT&T 6 Quantization Distortion (See Figure 13) CCITT G712 (Method 1) ° ± * Typical figures are with nominal 2 MT8960/61/62/63/64/65/66/67 ISO -CMOS Sym Min Typ PCS Voltages are with respect to GNDD unless otherwise stated. ...
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... MT8960/61/62/63/64/65/66/67 Transmit (A/D) Path (cont’d) Characteristics Quantization CCITT G712 Distortion (Method 2) (cont’d) AT&T (See Figure 13) 7 Idle Channel C-message Noise Psophometric 8 Single Frequency Noise 9 Harmonic Distortion (2nd or 3rd Harmonic) 10 Envelope Delay 11 Envelope Delay 1000-2600 Hz Variation With 600-3000 Hz Frequency 400-3200 Hz 12 ...
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... Harmonic Distortion (2nd or 3rd Harmonic) 10 Intermodulation CCITT G712 Distortion 2 tone AT & tone ° ± * Typical figures are with nominal 2 MT8960/61/62/63/64/65/66/67 ISO -CMOS - Voltages are with respect to GNDD unless otherwise stated. ± =2.5V 0.5%, GNDA=GNDD=0V, Clock Frequency = 2.048MHz, Ref Sym Min Typ* V OUT 4 ...
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... MT8960/61/62/63/64/65/66/67 Receive (D/A) Path (cont’d) Characteristics 11 Envelope Delay 12 Envelope Delay 1000-2600 Hz Variation with 600-3000 Hz Frequency 400-3200 Hz <200 Hz 13 Gain Relative to Gain @ 1004 Hz 200 Hz A (See Figure 11) 300-3000 Hz N 3300 Hz A 3400 Hz L 4000 Hz O ≥4600 Crosstalk A/D to D/A 15 Power Supply V DD ...
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... In typical applications, F1i will remain low for 8 cycles of C2i. However, the device will function normally as long are met at each positive edge of C2i. EH 90% C2i 50% Input 10% 90% DSTo 50% Output 10% t PLH 90% DSTi, CSTi 50% Input 10 MT8960/61/62/63/64/65/66/67 ISO -CMOS 8 CLOCK CYCLES (See Note PZL t PZH PLH ...
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... MT8960/61/62/63/64/65/66/67 SCALE B SCALE A PASSBAND ATTENUATION 0 -0.125 0. Attenuation Relative To Attenuation At 1 kHz (dB 5060 100 200 Figure 10 - Attenuation vs Frequency for Transmit (A/D) Filter SCALE A PASSBAND ATTENUATION 0 1 Attenuation Relative To Attenuation At 1 kHz (dB 100 200 Figure 11 - Attenuation vs Frequency for Receive (D/A) Filter ...
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... Bandlimited White Noise Test Signal 5b. CCITT Method 2 +1.5 +1.0 +0.5 +0.25 0 -60 -50 -0.25 -0.5 -1.0 -1.5 Sinusoidal Test Signal Figure 12 - Variation of Gain With Input Level 2 MT8960/61/62/63/64/65/66/67 -CMOS +1.0 +0.5 +0.25 0 -30 -20 -10 -0.25 -0.5 -1.0 CCITT End-To-End Spec -40 -30 -20 -10 1 Channel Spec 2 Input Level (dBm0) - Sinusiodal Test Signal 1 Channel Spec ...
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... MT8960/61/62/63/64/65/66/67 6a. CCITT Method 29.3 20 14.3 12 -60 -55 -50 6b. CCITT Method 25.4 24 -60 -50 Figure 13 - Signal to Total Distortion Ratio vs Input Level 6-38 2 ISO -CMOS 35.6 33.9 33.9 32.2 27.6 -20 -40 -34 -30 -27 Input Level (dBm0) 36.4 35.3 33.0 30.4 29.3 27.0 22.0 -40 -30 -20 Input Level (dBm0) 1 Channel Spec 2 28.0 26.3 CCITT End-To-End Spec - Channel Spec 36 ...
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... Figure 14 - Envelope Delay Variation Frequency 5 4 *Relative to Fundamental Output power level with +3dBm0 input signal level at a frequency of 1.02kHz. Figure 15 - Overload Distortion (End-to-End) 2 MT8960/61/62/63/64/65/66/67 -CMOS 1000 1500 2000 Input Level (dBm0) CCITT ∫ Channel Spec (2800Hz) (2600Hz) ...
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... MT8960/61/62/63/64/65/66/67 Notes: 6-40 2 ISO -CMOS ...
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Package Outlines Notes Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) Plastic Dual-In-Line Packages (PDIP Suffix 8-Pin DIM Plastic Min Max A 0.210 (5.33) A 0.115 (2.92) ...
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Notes Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) Plastic Dual-In-Line Packages (PDIP Suffix 22-Pin DIM Plastic Min Max A 0.210 (5.33) A 0.125 (3.18) 0.195 ...
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North America - West Coast Tel: (858) 675-3400 Fax: (858) 675-3450 Tel: +65 333 6193 Fax: +65 333 6192 Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) ...