MT8JTF12864HY-1G1 Micron, MT8JTF12864HY-1G1 Datasheet - Page 8

• Manufacturer Part Number: MT8JTF12864HY-1G1
• Description: 1GB DDR3 SDRAM SODIMM
• Manufacturer: Micron

General Description
Fly-By Topology
PDF: 09005aef82b36df5
Rev. C 8/09 EN
DDR3 SDRAM modules are high-speed, CMOS dynamic random access memory mod-
ules that use internally configured 8-bank DDR3 SDRAM devices. DDR3 SDRAM mod-
ules use DDR architecture to achieve high-speed operation. DDR3 architecture is
essentially an 8n-prefetch architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM
module effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the
internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data trans-
fers at the I/O pins.
DDR3 modules use two sets of differential signals: DQS, DQS# to capture data and CK
and CK# to capture commands, addresses, and control signals. Differential clocks and
data strobes ensure exceptional noise immunity for these signals and provide precise
crossing points to capture input signals.
DDR3 modules use faster clock speeds than earlier DDR technologies, making signal
quality more important than ever. For improved signal quality, the clock, control, com-
mand, and address buses have been routed in a fly-by topology, where each clock,
control, command, and address pin on each DRAM is connected to a single trace and
terminated (rather than a tree structure, where the termination is off the module near
the connector). Inherent to fly-by topology, the timing skew between the clock and DQS
signals can be easily accounted for by using the write-leveling feature of DDR3.
1GB, 2GB (x64, SR) 204-Pin DDR3 SDRAM SODIMM
8
Micron Technology, Inc. reserves the right to change products or specifications without notice.
General Description
©2007 Micron Technology, Inc. All rights reserved.