CS8406 Cirrus Logic, CS8406 Datasheet - Page 29
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CS8406
Manufacturer Part Number
CS8406
Description
192 KHZ DIGITAL AUDIO INTERFACE TRANSMITTER
Manufacturer
Cirrus Logic
Datasheet
1.CS8406.pdf
(43 pages)
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8.13 User Data Buffer Control (13h)
8.14 Channel Status bit or User bit Data Buffer (20h - 37h)
Either the channel status data buffer E or the separate user bit data buffer E (provided UBM bits are set to block
mode) is accessible through these register addresses.
8.15 CS8406 I.D. and Version Register (7Fh) (Read Only)
DS580F1
ID3
7
0
7
UD - User bit data source specifier
UBM1:0 - Sets the operating mode of the AES3 User bit manager
EFTUI - E to F U-data buffer transfer inhibit bit (valid in block mode only).
Default = ‘0’
0 - U Pin is the source of transmitted U data
1 - U data buffer is the source of transmitted U data
Default = ‘00’
00 - Transmit all zeros mode
01 - Block mode
10 - Reserved
11 - Reserved
Default = ‘0’
0 - Allow U-data E to F buffer transfers
1 - Inhibit U-data E to F buffer transfers
ID[3:0] - ID code for the CS8406. Permanently set to 1110
VER[3:0] = 0001 (revision A)
VER[3:0] = 0010 (revision B)
ID2
6
0
6
ID1
5
0
5
ID0
UD
4
4
UBM1
VER3
3
3
UBM0
VER2
2
2
VER1
1
1
0
CS8406
EFTUI
VER0
0
0
29