C1853CT NEC, C1853CT Datasheet - Page 20

• Manufacturer Part Number: C1853CT
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• Manufacturer: NEC

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3.2.2 Serial data transfer
(the data of subaddress 01H to 08H, bit D6 is “1”).
the data of SA
stop condition. Finally, it transfers stop condition and terminates.
of it.
3.2.3 Acknowledge
succeeded or not. The master CPU judges it from “High” and “Low” of acknowledge condition.
transfer or forced release of bus as NAK state.
side is finished in read state.
20
The following is the format in the case of transferring 8 bytes data at one time by using automatic increment function
Remark STA: Start, W: Write mode, ACK: Acknowledge, STP: Stop
The master CPU transfers “00H” as subaddress SA
The increments of the subaddress of the PC1853 stops automatically when the subaddress comes to “08H” inside
On I
When this acknowledge period is “Low”, it means success. And when the condition is “High”, it means failure of
The condition of being NAK state is when wrong slave address is transferred to slave IC or data transfer from slave
S
T
A
2
C bus, acknowledge bit is added to the 9th bit after the data in order to judge whether data transfer has been
SLAVE
ADDRESS
0
after subaddress, and then transfers the data of SA
W
A
C
K
SUB
ADDRESS
A
C
K
DATA1
0
after start and slave address like above figure. It transfers
A
C
K
DATA2
1
, SA
2
..., SA
A
C
K
8
continuously without transferring
DATA9
A
C
K
S
P
T
PC1853