74LVC1G74DC,125 NXP Semiconductors, 74LVC1G74DC,125 Datasheet - Page 4

• Manufacturer Part Number: 74LVC1G74DC,125
• Description: IC SNGL D FF POS-EDG TRIG 8VSSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVCr
• Type: D-Typer

Specifications of 74LVC1G74DC,125

• Output Type: Differential
• Package / Case: US8, 8-VSSOP
• Function: Set(Preset) and Reset
• Number Of Elements: 1
• Number Of Bits Per Element: 1
• Frequency - Clock: 200MHz
• Trigger Type: Positive Edge
• Current - Output High, Low: 32mA, 32mA
• Voltage - Supply: 1.65 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 1
• Logic Family: 74LVC
• Logic Type: CMOS
• Polarity: Inverting/Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 13.4 ns
• High Level Output Current: - 32 mA
• Low Level Output Current: 32 mA
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 1.65 V
• Technology: CMOS
• Number Of Bits: 1
• Number Of Elements: 1
• Clock-edge Trigger Type: Positive-Edge
• Operating Supply Voltage (typ): 1.8/2.5/3.3/5V
• Package Type: VSSOP
• Operating Supply Voltage (min): 1.65V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Delay Time - Propagation: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4494-2; 74LVC1G74DC-G; 74LVC1G74DC-G; 935274973125

NXP Semiconductors
6. Pinning information
74LVC1G74
Product data sheet
Fig 4.
Fig 6.
Pin configuration SOT505-2 and SOT765-1
Pin configuration SOT996-2
GND
CP
Q
D
GND
CP
Q
D
1
2
3
4
6.1 Pinning
1
2
3
4
Transparent top view
74LVC1G74
74LVC1G74
001aab659
8
7
6
5
001aah948
All information provided in this document is subject to legal disclaimers.
V
SD
RD
Q
8
7
6
5
CC
V
SD
RD
Q
CC
Single D-type flip-flop with set and reset; positive edge trigger
Rev. 9 — 5 August 2010
Fig 5.
Fig 7.
Pin configuration SOT833-1, SOT1089,
SOT1116 and SOT1203
Pin configuration SOT902-1
terminal 1
index area
RD
SD
GND
Q
CP
Q
D
Transparent top view
1
2
3
74LVC1G74
Transparent top view
1
2
3
4
74LVC1G74
001aab658
74LVC1G74
8
7
6
5
V
SD
RD
Q
CC
© NXP B.V. 2010. All rights reserved.
7
6
5
001aaf641
CP
D
Q
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